JAJSRS6A October 2023 – July 2024 MSPM0C1103-Q1 , MSPM0C1104-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
fADCCLK | ADC clock frequency | 12 | 24 | MHz | |||
tADC trigger | Software trigger minimum width | 3 | ADCCLK cycles | ||||
tSample_step | Sampling time for step input | 12-bit mode, RS = 50Ω, Cpext = 10pF | 0.166 | µs | |||
tSample_VREF | Sample time with VREF | ADC CHANNEL=12,12-bit mode, VDD as reference | 4 | µs | |||
tSample_SupplyMon | Sample time with Supply Monitor (VDD/3) | 3 | µs |