JAJSRS4B October   2023  – May 2024 MSPM0C1103 , MSPM0C1104

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 機能ブロック図
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 ADC
      1. 7.11.1 Electrical Characteristics
      2. 7.11.2 Switching Characteristics
      3. 7.11.3 Linearity Parameters
      4. 7.11.4 Typical Connection Diagram
    12. 7.12 Temperature Sensor
    13. 7.13 VREF
      1. 7.13.1 Voltage Characteristics
      2. 7.13.2 Electrical Characteristics
    14. 7.14 I2C
      1. 7.14.1 I2C Characteristics
      2. 7.14.2 I2C Filter
      3. 7.14.3 I2C Timing Diagram
    15. 7.15 SPI
      1. 7.15.1 SPI
      2. 7.15.2 SPI Timing Diagrams
    16. 7.16 UART
    17. 7.17 TIMx
    18. 7.18 Windowed Watchdog Characteristics
    19. 7.19 Emulation and Debug
      1. 7.19.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0C110x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 CRC
    16. 8.16 UART
    17. 8.17 SPI
    18. 8.18 I2C
    19. 8.19 WWDT
    20. 8.20 Timers (TIMx)
    21. 8.21 Device Analog Connections
    22. 8.22 Input/Output Diagrams
    23. 8.23 Serial Wire Debug Interface
    24. 8.24 Device Factory Constants
    25. 8.25 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DYY|16
  • RUK|20
  • DDF|8
  • DSG|8
  • PW|20
  • DGS|20
サーマルパッド・メカニカル・データ
発注情報

8.2.1 Functionality by Operating Mode (MSPM0C110x)

Table 8-1 lists the supported functionality in each operating mode.

Functional key:

  • EN: The function is enabled in the specified mode.
  • DIS: The function is disabled (either clock or power gated) in the specified mode, but the function's configuration is retained.
  • OPT: The function is optional in the specified mode, and remains enabled if configured to be enabled.
  • NS: The function is not automatically disabled in the specified mode, but use of the function is not supported.
  • OFF: The function is fully powered off in the specified mode, and no configuration information is retained.
Table 8-1 Supported Functionality by Operating Mode
Operating ModeRUNSLEEPSTOPSTANDBYSHUTDOWN
RUN0RUN1RUN2SLEEP0SLEEP1SLEEP2STOP0STOP2STANDBY0STANDBY1
OscillatorsSYSOSCENENDISENENDISOPT(1)DISDISDISOFF
LFOSCENOFF
ClocksCPUCLK24M32k32kDISOFF
MCLK to PD124M32k32k24M32k32kDISOFF
ULPCLK to PD024M32k32k24M32k32k4M(1)32kDISOFF
ULPCLK to TIMG14, TIMG824M32k32k24M32k32k4M(1)32kOFF
MFCLKOPTDISOPTDISOPTDISOFF
LFCLK32kDISOFF
LFCLK to TIMG14, TIMG832kOFF
MCLK MonitorOPTDISOFF
PMUPOR MonitorEN
BOR MonitorENOFF
Core RegulatorFull driveLow driveOFF
Core FunctionsCPUENDISOFF
DMAOPTNS (triggers supported)OFF
FlashENOPTDISOFF
SRAMENOPTDISOFF
PD1 PeripheralsSPI0OPTDISOFF
CRCOPTDISOFF
PD0 Peripherals TIMA0 OPT OFF
TIMG8OPTOFF
TIMG14OPTOFF
UART0OPTOPT(2)OFF
I2C0OPTOPT(2)OFF
GPIOAOPTOPT(2)OFF
WWDT0OPTDISOFF
AnalogADC0OPTNS (triggers supported)OFF
VREFOPTNSOFF
IOMUX and IO WakeupENDIS
Wake SourcesN/AANY IRQPD0 IRQ NRST, SWD
(1) If STOP0 is entered from RUN1 (SYSOSC enabled but MCLK sourced from LFCLK), SYSOSC remains enabled as it was in RUN1, and ULPCLK remains at 32kHz as it was in RUN1. If STOP0 is entered from RUN2 (SYSOSC was disabled and MCLK was sourced from LFCLK), SYSOSC remains disabled as it was in RUN2, and ULPCLK remains at 32kHz as it was in RUN2.
(2) When using the STANDBY1 policy for STANDBY, only TIMG8, TIMG14 and TIMA0 are clocked. Other PD0 peripherals can generate an asynchronous fast clock request upon external activity but are not actively clocked.