JAJSCO7A November   2016  – November 2017 MUX506 , MUX507

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Dual Supply
    6. 6.6 Electrical Characteristics: Single Supply
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1  Truth Tables
    2. 7.2  On-Resistance
    3. 7.3  Off Leakage
    4. 7.4  On-Leakage Current
    5. 7.5  Transition Time
    6. 7.6  Break-Before-Make Delay
    7. 7.7  Turn-On and Turn-Off Time
    8. 7.8  Charge Injection
    9. 7.9  Off Isolation
    10. 7.10 Channel-to-Channel Crosstalk
    11. 7.11 Bandwidth
    12. 7.12 THD + Noise
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Ultralow Leakage Current
      2. 8.3.2 Ultralow Charge Injection
      3. 8.3.3 Bidirectional Operation
      4. 8.3.4 Rail-to-Rail Operation
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage Supply VDD –0.3 40 V
VSS –40 0.3
VDD – VSS 40
Digital pins(2): EN, A0, A1, A2, A3 VSS – 0.3 VDD + 0.3
Analog pins(2): Sx, SxA, SxB, D, DA, DB VSS – 2 VDD + 2
Current(3) –30 30 mA
Temperature Operating, TA –55 150 °C
Junction, TJ 150
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage limits are valid if current is limited to ±30 mA.
(3) Only one pin at a time.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDD(1) Positive power-supply voltage Dual supply 5 18 V
Single supply 10 36
VSS(2) Negative power-supply voltage (dual supply) –5 –18 V
VDD – VSS Supply voltage 10 36 V
VS Source pins voltage(3) VSS VDD V
VD Drain pins voltage VSS VDD V
VEN Enable pin voltage VSS VDD V
VA Address pins voltage VSS VDD V
ICH Channel current (TA = 25°C) –25 25 mA
TA Operating temperature –40 125 °C
(1) When VSS = 0 V, VDD can range from 10 V to 36 V.
(2) VDD and VSS can be any value as long as 10 V ≤ (VDD – VSS) ≤ 36 V.
(3) VS is the voltage on all the S pins.

6.4 Thermal Information

THERMAL METRIC(1) MUX50x UNIT
PW (TSSOP) DW (SOIC)
28 PINS 28 PINS
RθJA Junction-to-ambient thermal resistance 79.8 53.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 24.0 30.1 °C/W
RθJB Junction-to-board thermal resistance 37.6 28.5 °C/W
ψJT Junction-to-top characterization parameter 1.2 9.0 °C/W
ψJB Junction-to-board characterization parameter 37.1 28.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics: Dual Supply

at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG SWITCH
Analog signal range TA = –40°C to +125°C VSS VDD V
RON On-resistance VS = 0 V, IS = –1 mA 125 170 Ω
VS = ±10 V, IS = –1 mA 145 200
TA = –40°C to +85°C 230
TA = –40°C to +125°C 250
ΔRON On-resistance mismatch between channels VS = ±10 V, IS = –1 mA 6 9 Ω
TA = –40°C to +85°C 14
TA = –40°C to +125°C 16
RFLAT On-resistance flatness VS = 10 V, 0 V, –10 V 20 45 Ω
TA = –40°C to +85°C 53
TA = –40°C to +125°C 58
On-resistance drift VS = 0 V 0.62 Ω/°C
IS(OFF) Input leakage current Switch state is off,
VS = ±10 V, VD = ±10 V(2)		 –1 –0.001 1 nA
TA = –40°C to +85°C –10 10
TA = –40°C to +125°C –25 25
ID(OFF) Output off-leakage current Switch state is off,
VS = ±10 V, VD = ±10 V(2)		 –1 –0.01 1 nA
TA = -40°C to +85°C –10 10
TA = -40°C to +125°C –25 25
ID(ON) Output on-leakage current Switch state is on,
VD = ±10 V, VS = floating		 –1 –0.01 1 nA
TA = –40°C to +85°C –10 10
TA = –40°C to +125°C –50 50
LOGIC INPUT
VIH Logic voltage high 2 V
VIL Logic voltage low 0.8 V
ID Input current 0.1 µA
SWITCH DYNAMICS(1)
tON Enable turn-on time VS = ±10 V, RL = 300 Ω,
CL= 35 pF		 82 136 ns
TA = –40°C to +85°C 145
TA = –40°C to +125°C 151
tOFF Enable turn-off time VS = ±10 V, RL = 300 Ω,
CL= 35 pF		 63 78 ns
TA = –40°C to +85°C 89
TA = –40°C to +125°C 97
tt Transition time VS = 10 V, RL = 300 Ω,
CL= 35 pF, 		97 143 ns
TA = –40°C to +85°C 151
TA = –40°C to +125°C 157
tBBM Break-before-make time delay VS = 10 V, RL = 300 Ω, CL= 35 pF, TA = –40°C to +125°C 30 54 ns
QJ Charge injection CL = 1 nF, RS = 0 Ω VS = 0 V TSSOP package 0.31 pC
SOIC package 0.67
VS = –15 V to +15 V TSSOP package ±0.9
SOIC package ±1.1
Off-isolation RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz 		Nonadjacent channel to D, DA, DB TSSOP package –98 dB
SOIC package –94
Adjacent channel to D, DA, DB TSSOP package –94
SOIC package –88
Channel-to-channel crosstalk RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz		 Nonadjacent channels TSSOP package –100 dB
SOIC package –96
Adjacent channels TSSOP package –88
SOIC package –83
CS(OFF) Input off-capacitance f = 1 MHz, VS = 0 V 2.1 3 pF
CD(OFF) Output off-capacitance f = 1 MHz, VS = 0 V MUX506 11.1 12.2 pF
MUX507 6.4 7.5
CS(ON), CD(ON) Output on-capacitance f = 1 MHz, VS = 0 V MUX506 13.5 15 pF
MUX507 8.7 10.2
POWER SUPPLY
VDD supply current All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V, 		45 59 µA
TA = –40°C to +85°C 62
TA = –40°C to +125°C 85
VSS supply current All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V, 		26 34 µA
TA = –40°C to +85°C 37
TA = –40°C to +125°C 58
(1) Specified by design; not subject to production testing.
(2) When VS is positive, VD is negative, and vice versa.

6.6 Electrical Characteristics: Single Supply

at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG SWITCH
Analog signal range TA = –40°C to +125°C VSS VDD V
RON On-resistance VS = 10 V, IS = –1 mA 235 340 Ω
TA = –40°C to +85°C 390
TA = –40°C to +125°C 430
ΔRON On-resistance match VS = 10 V, IS = –1 mA 7 20 Ω
TA = –40°C to +85°C 35
TA = –40°C to +125°C 40
On-resistance drift VS = 10 V 1.07 Ω/°C
IS(OFF) Input leakage current Switch state is off,
VS = 1 V and VD = 10 V,
or VS = 10 V and VD = 1 V(1)		 –1 0.001 1 nA
TA = –40°C to +85°C –10 10
TA = –40°C to +125°C –25 25
ID(OFF) Output off leakage current Switch state is off,
VS = 1 V and VD = 10 V,
or VS = 10 V and VD = 1 V(1)		 –1 0.01 1 nA
TA = –40°C to +85°C –10 10
TA = –40°C to +125°C –25 25
ID(ON) Output on leakage current Switch state is on,
VD = 1 V and 10 V, VS = floating		 –1 0.02 1 nA
TA = –40°C to +85°C –10 10
TA = –40°C to +125°C –50 50
LOGIC INPUT
VIH Logic voltage high 2.0 V
VIL Logic voltage low 0.8 V
ID Input current 0.1 µA
SWITCH DYNAMIC CHARACTERISTICS(2)
tON Enable turn-on time VS = 8 V, RL = 300 Ω,
CL= 35 pF		 90 145 ns
TA = –40°C to +85°C 145
TA = –40°C to +125°C 149
tOFF Enable turn-off time VS = 8 V, RL = 300 Ω,
CL= 35 pF		 66 84 ns
TA = –40°C to +85°C 94
TA = –40°C to +125°C 102
tt Transition time VS = 8 V, CL= 35 pF 107 147 ns
VS = 8 V, RL = 300 Ω,
CL= 35 pF, 		TA = –40°C to +85°C 153
VS = 8 V, RL = 300 Ω,
CL= 35 pF, 		TA = –40°C to +125°C 155
tBBM Break-before-make time delay VS = 8 V, RL = 300 Ω, CL= 35 pF, TA = –40°C to +125°C 30 54 ns
QJ Charge injection CL = 1 nF, RS = 0 Ω VS = 6 V TSSOP package 0.12 pC
SOIC package 0.38
VS = 0 V to 12 V TSSOP ±0.17
SOIC package ±0.48
Off-isolation RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz 		Nonadjacent channel to D, DA, DB TSSOP package –97 dB
SOIC package –94
Adjacent channel to D, DA, DB TSSOP package –94
SOIC package –88
Channel-to-channel crosstalk RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz		 Nonadjacent channels TSSOP package –100 dB
SOIC package –99
Adjacent channels TSSOP -88
SOIC package -83
CS(OFF) Input off-capacitance f = 1 MHz, VS = 6 V 2.4 3.4 pF
CD(OFF) Output off-capacitance f = 1 MHz, VS = 6 V MUX506 14 15.4 pF
MUX507 7.8 9.1
CS(ON), CD(ON) Output on-capacitance f = 1 MHz, VS = 6 V MUX506 16.2 18 pF
MUX507 9.9 11.6
POWER SUPPLY
VDD supply current All VA = 0 V or 3.3 V,
VS= 0 V, VEN = 3.3 V		 41 59 µA
TA = –40°C to +85°C 62
TA = –40°C to +125°C 83
VSS supply current All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V		 22 34 µA
TA = –40°C to +85°C 37
TA = –40°C to +125°C 57
(1) When VS is 1 V, VD is 10 V, and vice versa.
(2) Specified by design, not subject to production test.

6.7 Typical Characteristics

at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
MUX506 MUX507 D001_SLASED9.gif
Figure 1. On-Resistance vs Source or Drain Voltage
MUX506 MUX507 D003_SLASED9.gif
Figure 3. On-Resistance vs Source or Drain Voltage
MUX506 MUX507 D024_SLASED9.gif
Figure 5. On-Resistance vs Source or Drain Voltage
MUX506 MUX507 D025_SLASED9.gif
VDD = 24 V, VSS = 0 V
Figure 7. On-Resistance vs Source or Drain Voltage
MUX506 MUX507 D006_SLASED9.gif
VDD = 15 V, VSS = –15 V
Figure 9. Leakage Current vs Temperature
MUX506 MUX507 D011_SLASED9.gif
MUX506, source-to-drain
Figure 11. Charge Injection vs Source Voltage
MUX506 MUX507 D008_SLASED9.gif
Drain-to-source
Figure 13. Charge Injection vs Drain Voltage
MUX506 MUX507 D012_SLASED9.gif
Figure 15. Off Isolation vs Frequency
MUX506 MUX507 D014_SLASED9.gif
Figure 17. THD+N vs Frequency
MUX506 MUX507 D015_SLASED9.gif
MUX506, VDD = 15 V, VSS = –15 V
Figure 19. Capacitance vs Source Voltage
MUX506 MUX507 D017_SLASED9.gif
MUX506, VDD = 30 V, VSS = 0 V
Figure 21. Capacitance vs Source Voltage
MUX506 MUX507 D019_SLASED9.gif
MUX506, VDD = 12 V, VSS = 0 V
Figure 23. Capacitance vs Source Voltage
MUX506 MUX507 D028_SLASED9.gif
Figure 25. Source Current vs Drain Current
MUX506 MUX507 D002_SLASED9.gif
VDD = 15 V, VSS = –15 V
Figure 2. On-Resistance vs Source or Drain Voltage
MUX506 MUX507 D004_SLASED9.gif
VDD = 12 V, VSS = 0 V
Figure 4. On-Resistance vs Source or Drain Voltage
MUX506 MUX507 D005_SLASED9.gif
Figure 6. On-Resistance vs Source or Drain Voltage
MUX506 MUX507 D026_SLASED9.gif
VDD = 12 V, VSS = –12 V
Figure 8. On-Resistance vs Source or Drain Voltage
MUX506 MUX507 D007_SLASED9.gif
Þ
VDD = 12 V, VSS = 0 V
Figure 10. Leakage Current vs Temperature
MUX506 MUX507 D027_SLASED9.gif
MUX507, source-to-drain
Figure 12. Charge Injection vs Source Voltage
MUX506 MUX507 D010_SLASED9.gif
Figure 14. Turn-On and Turn-Off Times vs Temperature
MUX506 MUX507 D013_SLASED9.gif
Figure 16. Crosstalk vs Frequency
MUX506 MUX507 D021_SLASED9.gif
Figure 18. On Response vs Frequency
MUX506 MUX507 D016_SLASED9.gif
MUX507, VDD = 15 V, VSS = –15 V
Figure 20. Capacitance vs Source Voltage
MUX506 MUX507 D018_SLASED9.gif
MUX507, VDD = 30 V, VSS = 0 V
Figure 22. Capacitance vs Source Voltage
MUX506 MUX507 D020_SLASED9.gif
MUX507, VDD = 12 V, VSS = 0 V
Figure 24. Capacitance vs Source Voltage