SLOS070D July   1979  – November 2014 NE5534 , NE5534A , SA5534 , SA5534A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Operating Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Offset-Voltage Null Capability
      2. 8.3.2 Slew Rate
      3. 8.3.3 Common-Mode Rejection Ratio
      4. 8.3.4 Unity-Gain Bandwidth
      5. 8.3.5 External Compensation Capability
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 General Application
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Swing
        2. 9.2.2.2 Supply and Input Voltage
      3. 9.2.3 Application Curves for Output Characteristics
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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発注情報

10 Power Supply Recommendations

The NE5534 and SA5534 devices are specified for operation from ±5 to ±15 V; many specifications apply from 0°C to 70°C for the NE5534 device and –40°C to 85°C for the SA5534 device.

CAUTION

Supply voltages larger than ±22 V can permanently damage the device (see the Absolute Maximum Ratings).

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout Guidelines.