JAJSRJ1A June   2011  – February 2024 OPA564-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adjustable Current Limit
        1. 7.3.1.1 Setting the Current Limit
      2. 7.3.2 Enable and Shutdown (E/S) Pin
      3. 7.3.3 Input Protection
      4. 7.3.4 Output Shutdown
      5. 7.3.5 Microcontroller Compatibility
      6. 7.3.6 Current Limit Flag
      7. 7.3.7 Thermal Protection
      8. 7.3.8 Junction Temperature Measurement Using TSENSE
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Basic Configuration
      2. 8.1.2 Output-Stage Compensation
      3. 8.1.3 Output Protection
      4. 8.1.4 Power Dissipation and Safe Operating Area
    2. 8.2 Typical Applications
      1. 8.2.1 Improved Howland Current Pump
      2. 8.2.2 Programmable Power Supply
      3. 8.2.3 Powerline Communication
      4. 8.2.4 Motor-Drive Circuit
      5. 8.2.5 DC Motor-Speed Controller (Without Tachometer)
      6. 8.2.6 Generating VDIG
      7. 8.2.7 Temperature Measurement
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermally Enhanced PowerPAD™ Integrated Circuit Package
          1. 8.4.1.1.1 Bottom-Side Thermal Pad Assembly Process
  10. Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報
Bottom-Side Thermal Pad Assembly Process
  1. The thermal pad must be connected to the most negative supply of the device, V–.
  2. Prepare the PCB with a top-side etch pattern, as shown in the attached thermal land pattern mechanical drawing. Use etch for the leads as well as etch for the thermal land.
  3. Place the recommended number of holes (or thermal vias) in the area of the thermal pad, as seen in the attached thermal land pattern mechanical drawing. These holes are 13 mils (0.013in, or 330.2μm) in diameter. Keep the holes small so that solder wicking through the holes is not a problem during reflow.
  4. For optimized performance, place a small number of the holes under the package and outside the thermal pad area. These holes provide an additional heat path between the copper land and ground plane and are 25 mils (0.025in, or 635μm) in diameter. These holes can be larger because these holes are not in the area to be soldered; therefore, wicking is not a problem. This configuration is illustrated in the attached thermal land pattern mechanical drawing.
  5. Connect all holes, including those within the thermal pad area and outside the pad area, to the internal plane that is at the same voltage potential as V–.
  6. When connecting these holes to the internal plane, do not use the typical web or spoke via connection methodology (as Figure 8-16 shows). Web connections have a high thermal resistance connection that is useful for slowing heat transfer during soldering operations. This configuration makes the soldering of vias that have plane connections easier. However, in this application, low thermal resistance is desired for the most efficient heat transfer. Therefore, connect the holes under the PowerPAD integrated circuit package to the internal plane with a complete connection around the entire circumference of the plated through-hole.
  7. Leave the terminals of the package and the thermal pad area exposed through the top-side solder mask. Leave the 13‑mil holes exposed through the thermal pad area. Cover the larger 25‑mil holes outside the thermal pad area with solder mask.
  8. Apply solder paste to the exposed thermal pad area and all of the package terminals.
  9. With these preparatory steps completed, the PowerPAD integrated circuit package is simply placed in position and run through the solder-reflow operation as with any standard surface-mount component. This processing results in a device that is properly installed.

For detailed information on the PowerPAD integrated circuit package, including thermal modeling considerations and repair procedures, see the PowerPAD Thermally Enhanced Package technical brief, available at www.ti.com.

GUID-34701C95-8F6C-417B-B8E5-4F5FC1BE82D7-low.gif Figure 8-16 Via Connection Methods