JAJSQK2A November   2023  – July 2024 OPA2892 , OPA892

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Offset Nulling
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving a Capacitive Load
      2. 7.1.2 General Configuration
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 General PowerPAD™ Integrated Circuit Package Design Considerations
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • D|8
サーマルパッド・メカニカル・データ
発注情報

Detailed Design Procedure

As detailed by Figure 7-4, the example design is a common non-inverting op-amp configuration. In this design example, the spit ±15 V supplies are bypassed by a pair of capacitors as discussed in Section 7.4.1. Although not explicitly shown, a optional resistor equal to RF || RG can be added from the noninverting input to ground to keep the inputs balanced to help mitigate input bias current impact.

Set the gain to 10 V/V by the proper selection of the two resistors using equation Equation 2. In this example, set the ratio of the resistance to 9 to obtain the design goal of a gain of 10. There exists a second degree of freedom that allows the absolute value to be somewhat arbitrary while maintaining the specified ratio of resistor values. Increasing feedback resistance leads to an increase in the amount of overshoot in the small-signal frequency response (see Figure 5-1). In the time domain, the impact shows up as and increase in ringing and settling time for step-function input signals. If the resistances are very small, power dissipation effects increase.

Equation 2. g a i n =   V O V I = 1 + R F R G

The best practice is to chose the resistors to be in of moderate values to avoid the detrimental effects at both extremes. Choosing RF = 220 Ω is a good compromise in between these two extremes. Using Equation 2, the corresponding gain resistor is found to be 24 Ω. The amount of small-signal peaking is a modest 1.5 dB (see Figure 5-1), which meets the design goal.

A unique feature of this amplifier family is the output stage has been designed to drive a substantial amount of output current. This choice allows for the OPAx892 to maintain significant bandwidth even with very large input signals. Figure 7-5 shows the modest reduction of bandwidth, even for output signals as large as 20 VPP. The time domain impact of this feature is a more precise amplification (that is, lower distortion) even for large dynamic range input signals.

Using the amplifier designed in this section, Figure 7-6 shows the measured components of THD down to the 5th harmonic. The figure shows that the 2nd harmonic dictates the THD performance, with the 4th harmonic being the next highest component. Other amplifiers can produce low distortion at lower input levels but distortion rapidly rises as the output amplitude rises. Figure 5-17 shows the harmonic distortion stays approximately constant, even at large values of output amplitude, making the OPAx892 a solid choice for large amplitude applications where distortion and noise are critical considerations.