8.5.1.3 SMBus Alert Response

The SMBus alert response provides a quick identification for which device issued the interrupt. Without this alert response capability, the processor does not know which device pulled the interrupt line when there are multiple slave devices connected.

The OPT3001-Q1 device is designed to respond to the SMBus alert response address, when in the latched window-style comparison mode (configuration register, latch field = 1). The OPT3001-Q1 device does not respond to the SMBus alert response when in transparent mode (configuration register, latch field = 0).

The response behavior of the OPT3001-Q1 device to the SMBus alert response is shown in Figure 26. When the interrupt line to the processor is pulled to active, the master can broadcast the alert response slave address (0001 1001b). Following this alert response, any slave devices that generated an alert identify themselves by acknowledging the alert response and sending their respective I²C address on the bus. The alert response can activate several different slave devices simultaneously. If more than one slave attempts to respond, bus arbitration rules apply. The device with the lowest address wins the arbitration. If the OPT3001-Q1 device loses the arbitration, the device does not acknowledge the I²C transaction and its INT pin remains in an active state, prompting the I²C master processor to issue a subsequent SMBus alert response. When the OPT3001-Q1 device wins the arbitration, the device acknowledges the transaction and sets its INT pin to inactive. The master can issue that same command again, as many times as necessary to clear the INT pin. See the Interrupt Reporting Mechanism Modes section for additional details of how the flags and INT pin are controlled. The master can obtain information about the source of the OPT3001-Q1 interrupt from the address broadcast in the above process. The flag high field (configuration register, bit 6) is sent as the final LSB of the address to provide the master additional information about the cause of the OPT3001-Q1 interrupt. If the master requires additional information, the result register or the configuration register can be queried. The flag high and flag low fields are not cleared upon an SMBus alert response.

1.

NOINDENT:

FH is the flag high field (FH) in the configuration register (see Table 10).

2.

NOINDENT:

A1 and A0 are determined by the ADDR pin; see Table 1.

Figure 26. Timing Diagram for SMBus Alert Response