JAJSC89A May   2016  – June 2016 OPT3002

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Automatic Full-Scale Range Setting
      2. 7.3.2 Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
      3. 7.3.3 I2C Bus Overview
        1. 7.3.3.1 Serial Bus Address
        2. 7.3.3.2 Serial Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Automatic Full-Scale Setting Mode
      2. 7.4.2 Interrupt Reporting Mechanism Modes
        1. 7.4.2.1 Latched Window-Style Comparison Mode
        2. 7.4.2.2 Transparent Hysteresis-Style Comparison Mode
        3. 7.4.2.3 End-of-Conversion Mode
        4. 7.4.2.4 End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
    5. 7.5 Programming
      1. 7.5.1 Writing and Reading
        1. 7.5.1.1 High-Speed I2C Mode
        2. 7.5.1.2 General-Call Reset Command
        3. 7.5.1.3 SMBus Alert Response
    6. 7.6 Register Maps
      1. 7.6.1 Internal Registers
        1. 7.6.1.1 Register Descriptions
          1. 7.6.1.1.1 Result Register (address = 00h)
          2. 7.6.1.1.2 Configuration Register (address = 01h) [reset = C810h]
          3. 7.6.1.1.3 Low-Limit Register (address = 02h) [reset = C0000h]
          4. 7.6.1.1.4 High-Limit Register (address = 03h) [reset = BFFFh]
          5. 7.6.1.1.5 Manufacturer ID Register (address = 7Eh) [reset = 5449h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Electrical Interface
      2. 8.1.2 Optical Interface
      3. 8.1.3 Compensation for the Spectral Response
    2. 8.2 Do's and Don'ts
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 ハンダ付けと取り扱いについての推奨事項
    2. 12.2 DNP (S-PDSO-N6)メカニカル図面

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DNP Package
6-Pin USON
Top View

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 VDD Power Device power. Connect to a 1.6-V to 3.6-V supply.
2 ADDR Digital input Address pin. This pin sets the LSBs of the I2C address.
3 GND Power Ground
4 SCL Digital input I2C clock. Connect with a 10-kΩ resistor to a 1.6-V to 5.5-V supply.
5 INT Digital output Interrupt output open-drain. Connect with a 10-kΩ resistor to a 1.6-V to 5.5-V supply.
6 SDA Digital input/output I2C data. Connect with a 10-kΩ resistor to a 1.6-V to 5.5-V supply.