JAJSC89A May   2016  – June 2016 OPT3002

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Automatic Full-Scale Range Setting
      2. 7.3.2 Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
      3. 7.3.3 I2C Bus Overview
        1. 7.3.3.1 Serial Bus Address
        2. 7.3.3.2 Serial Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Automatic Full-Scale Setting Mode
      2. 7.4.2 Interrupt Reporting Mechanism Modes
        1. 7.4.2.1 Latched Window-Style Comparison Mode
        2. 7.4.2.2 Transparent Hysteresis-Style Comparison Mode
        3. 7.4.2.3 End-of-Conversion Mode
        4. 7.4.2.4 End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
    5. 7.5 Programming
      1. 7.5.1 Writing and Reading
        1. 7.5.1.1 High-Speed I2C Mode
        2. 7.5.1.2 General-Call Reset Command
        3. 7.5.1.3 SMBus Alert Response
    6. 7.6 Register Maps
      1. 7.6.1 Internal Registers
        1. 7.6.1.1 Register Descriptions
          1. 7.6.1.1.1 Result Register (address = 00h)
          2. 7.6.1.1.2 Configuration Register (address = 01h) [reset = C810h]
          3. 7.6.1.1.3 Low-Limit Register (address = 02h) [reset = C0000h]
          4. 7.6.1.1.4 High-Limit Register (address = 03h) [reset = BFFFh]
          5. 7.6.1.1.5 Manufacturer ID Register (address = 7Eh) [reset = 5449h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Electrical Interface
      2. 8.1.2 Optical Interface
      3. 8.1.3 Compensation for the Spectral Response
    2. 8.2 Do's and Don'ts
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 ハンダ付けと取り扱いについての推奨事項
    2. 12.2 DNP (S-PDSO-N6)メカニカル図面

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
Voltage VDD to GND –0.5 6 V
SDA, SCL, INT, and ADDR to GND –0.5 6
Current into any pin 10 mA
Temperature Junction, TJ 150 °C
Storage, Tstg –65 150(2)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Long exposure to temperatures higher than 105°C can cause package discoloration, spectral distortion, and measurement inaccuracy.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Operating power-supply voltage 1.6 3.6 V
Operating temperature –40 85 °C

6.4 Thermal Information

THERMAL METRIC(1) OPT3002 UNIT
DNP (USON)
6 PINS
RθJA Junction-to-ambient thermal resistance 71.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 45.7 °C/W
RθJB Junction-to-board thermal resistance 42.2 °C/W
ψJT Junction-to-top characterization parameter 2.4 °C/W
ψJB Junction-to-board characterization parameter 42.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 17.0 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at TA = 25°C, VDD = 3.3 V, 800-ms conversion time (CT = 1)(3), automatic full-scale range (RN[3:0] = 1100b(3)), 505-nm LED stimulus, and normal-angle incidence of light (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPTICAL
Peak irradiance spectral responsivity 505 nm
Resolution (LSB) at 505 nm Lowest full-scale range (FSR), RN[3:0] = 0000b(3) 1.2 nW/cm2(1)
Full-scale illuminance at 505 nm 10.064 mW/cm2(1)
Measurement output result 505-nm LED stimulus, FSR setting = 628,992 (nW/cm2), 153.6 (nW/cm2) per ADC code (RN[3:0] = 0111)(3) 384,000 nW/cm2(1)
2500 ADC codes
2 klux white LED stimulus, FSR setting = 628,992 (nW/cm2), 153.6 (nW/cm2) per ADC code (RN[3:0] = 0111)(3)(4) 2250 2500 2750 ADC codes
Relative accuracy between gain ranges(2) 0.2%
Infrared response (850 nm) relative to response at 505 nm(4) 20%
Linearity Input illuminance > 5000 nW/cm2 2%
Input illuminance < 5000 nW/cm2 5%
Dark condition, ADC output Lowest FSR, RN[3:0] = 0000b, 4914 (nW/cm2), 1.2 (nW/cm2) per ADC code 0 3 ADC codes
Half-power angle 50% of full-power reading 60 Degrees
PSRR Power-supply rejection ratio VDD at 3.6 V and 1.6 V 0.1 %/V(5)
POWER SUPPLY
VI²C I2C pullup resistor operating range I2C pullup resistor, VDD ≤ VI²C 1.6 5.5 V
IQ Quiescent current Dark Active, VDD = 3.6 V 1.8 2.5 µA
Shutdown (M[1:0] = 00)(3), VDD = 3.6 V 0.3 0.47
Full-scale range Active, VDD = 3.6 V 3.7
Shutdown,
(M[1:0] = 00)(3)		 0.4
POR Power-on-reset threshold TA = 25°C 0.8 V
DIGITAL
I/O pin capacitance 3 pF
Total integration time(6) (CT = 1)(3), 800-ms mode, fixed FSR 720 800 880 ms
(CT = 0)(3), 100-ms mode, fixed FSR 90 100 110
VIL Low-level input voltage
(SDA, SCL, and ADDR)		 0 0.3 × VDD V
VIH High-level input voltage
(SDA, SCL, and ADDR)		 0.7 × VDD 5.5 V
IIL Low-level input current
(SDA, SCL, and ADDR)		 0.01 0.25(7) µA
VOL Low-level output voltage
(SDA and INT)		 IOL = 3 mA 0.32 V
IZH Output logic high, high-Z leakage current (SDA, INT) At VDD pin 0.01 0.25(7) µA
(1) All nW/cm2 units assume a 505-nm stimulus. To scale the LSB size, full-scale, and results at other wavelengths, see the Compensation for the Spectral Response section.
(2) Characterized by measuring fixed near-full-scale light levels on the higher adjacent full-scale range setting.
(3) Refers to a control field within the configuration register.
(4) Tested with the white LED calibrated to 2 klux and an 850-nm LED.
(5) PSRR is the percent change of the measured optical power output from its current value, divided by the change in power-supply voltage, as characterized by results from the 3.6-V and 1.6-V power supplies.
(6) The conversion time, from start of conversion until data are ready to be read, is the integration time plus 3 ms.
(7) The specified leakage current is dominated by the production test equipment limitations. Typical values are much smaller.

6.6 Timing Requirements(1)

MIN TYP MAX UNIT
I2C FAST MODE
fSCL SCL operating frequency 0.01 0.4 MHz
tBUF Bus free time between stop and start 1300 ns
tHDSTA Hold time after repeated start 600 ns
tSUSTA Setup time for repeated start 600 ns
tSUSTO Setup time for stop 600 ns
tHDDAT Data hold time 20 900 ns
tSUDAT Data setup time 100 ns
tLOW SCL clock low period 1300 ns
tHIGH SCL clock high period 600 ns
tRC and tFC Clock rise and fall time 300 ns
tRD and tFD Data rise and fall time 300 ns
tTIMEO Bus timeout period. If the SCL line is held low for this duration of time, then the bus state machine is reset. 28 ms
I2C HIGH-SPEED MODE
fSCL SCL operating frequency 0.01 2.6 MHz
tBUF Bus free time between stop and start 160 ns
tHDSTA Hold time after repeated start 160 ns
tSUSTA Setup time for repeated start 160 ns
tSUSTO Setup time for stop 160 ns
tHDDAT Data hold time 20 140 ns
tSUDAT Data setup time 20 ns
tLOW SCL clock low period 240 ns
tHIGH SCL clock high period 60 ns
tRC and tFC Clock rise and fall time 40 ns
tRD and tFD Data rise and fall time 80 ns
tTIMEO Bus timeout period. If the SCL line is held low for this duration of time, then the bus state machine is reset. 28 ms
(1) All timing parameters are referenced to low and high voltage thresholds of 30% and 70%, respectively, of the final settled value.
OPT3002 aij_I2C_Timing_R2.gif Figure 1. I2C Detailed Timing Diagram

6.7 Typical Characteristics

at TA = 25°C, VDD = 3.3 V, 800-ms conversion time (CT = 1), automatic full-scale range (RN[3:0] = 1100b), white LED, and normal-angle incidence of light (unless otherwise specified)
OPT3002 D001_SBOS745.gif
Figure 2. Spectral Response vs Wavelength
OPT3002 D007_SBOS745.gif
Input illuminance = 298,800 nW/cm2,
normalized to response of 314,496 nW/cm2 full-scale
Figure 4. Full-Scale-Range Matching (Highest 6 Ranges)
OPT3002 D008_SBOS745.gif
Figure 6. Normalized Response vs Temperature
OPT3002 D009_SBOS681.gif
Figure 8. Normalized Response vs Power-Supply Voltage
OPT3002 D011_SBOS745.gif
M[1:0] = 10b, illuminance derived from white LED
Figure 10. Supply Current in Active State vs
Input Illuminance
OPT3002 D013_SBOS681.gif
M[1:0] = 10b
Figure 12. Supply Current in Active State vs Temperature
OPT3002 D015_SBOS681.gif
SCL = SDA, continuously toggled at I2C frequency
Note: A typical application runs at a lower duty cycle and thus consumes a lower current.
Figure 14. Supply Current in Shutdown State vs Continuous I2C Frequency
OPT3002 D006_SBOS745.gif
Input illuminance = 3960 nW/cm2,
normalized to response of 4914 nW/cm2 full-scale
Figure 3. Full-Scale-Range Matching (Lowest 7 Ranges)
OPT3002 D016_SBOS745.gif
Average of 30 devices
Figure 5. Dark Response vs Temperature
OPT3002 D017_SBOS681.gif
Figure 7. Conversion Time vs Power Supply
OPT3002 D010_SBOS745.gif
Figure 9. Normalized Response vs Incidence Angle
OPT3002 D012_SBOS745.gif
M[1:0] = 00b, illuminance derived from white LED
Figure 11. Supply Current in Shutdown State vs
Input Illuminance
OPT3002 D014_SBOS681.gif
M[1:0] = 00b, input illuminance = 0 nW/cm2
Figure 13. Supply Current in Shutdown State vs Temperature