7.3.1 Automatic Full-Scale Range Setting

The OPT3002 has an automatic full-scale range setting feature that eliminates the need to predict and set the optimal range for the device. In this mode, the OPT3002 automatically selects the optimal full-scale range for the given lighting condition. The OPT3002 has a high degree of result matching between the full-scale range settings. This matching eliminates the problem of varying results or the need for range-specific, user-calibrated gain factors when different full-scale ranges are chosen. For further details, see the Automatic Full-Scale Setting Mode section.

7.3.2 Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms

The device has an interrupt reporting system that allows the processor connected to the I²C bus to go to sleep, or otherwise ignore the device results, until a user-defined event occurs that requires possible action. Alternatively, this same mechanism can also be used with any system that can take advantage of a single digital signal that indicates whether the light is above or below the levels of interest.

The interrupt event conditions are controlled by the high-limit and low-limit registers, as well as the configuration register latch and fault count fields. The results of comparing the result register with the high-limit register and low-limit register are referred to as fault events. The fault count field (configuration register, bits FC[1:0]) dictates how many consecutive same-result fault events are required to trigger an interrupt event and subsequently change the state of the interrupt reporting mechanisms (that is, the INT pin, the flag high field, and the flag low field). The latch field allows a choice between a latched window-style comparison and a transparent hysteresis-style comparison.

The INT pin has an open-drain output that requires the use of a pullup resistor. This open-drain output allows multiple devices with open-drain INT pins to be connected to the same line, thus creating a logical NOR or AND function between the devices. The polarity of the INT pin can be controlled with the polarity of the interrupt field in the configuration register. When the POL field is set to 0, the pin operates in an active low behavior that pulls the pin low when the INT pin becomes active. When the POL field is set to 1, the pin operates in an active high behavior and becomes high impedance, thus allowing the pin to go high when the INT pin becomes active.

Additional details of the interrupt reporting registers are described in the Interrupt Reporting Mechanism Modes and Internal Registers sections.

7.3.3 I²C Bus Overview

The OPT3002 offers compatibility with both I²C and SMBus interfaces. The I²C and SMBus protocols are essentially compatible with one another. The I²C interface is used throughout this document as the primary example with the SMBus protocol specified only when a difference between the two protocols is discussed.

The OPT3002 is connected to the bus with two pins: an SCL clock input pin and an SDA open-drain bidirectional data pin. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates start and stop conditions. To address a specific device, the master initiates a start condition by pulling the data signal line (SDA) from a high logic level to a low logic level when SCL is high. All slaves on the bus shift in the slave address byte on the SCL rising edge, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an acknowledge bit by pulling SDA low.

Data transfer is then initiated and eight bits of data are sent, followed by an acknowledge bit. During data transfer, SDA must remain stable when SCL is high. Any change in SDA when SCL is high is interpreted as a start or stop condition. When all data are transferred, the master generates a stop condition, as indicated by pulling SDA from low to high when SCL is high. The OPT3002 includes a 28-ms timeout on the I²C interface to prevent locking up the bus. If the SCL line is held low for this duration of time, then the bus state machine is reset.

7.4.1 Automatic Full-Scale Setting Mode

The OPT3002 has an automatic full-scale-range setting mode that eliminates the need for a user to predict and set the optimal range for the device. This mode is entered when the configuration register range number field (RN[3:0]) is set to 1100b.

The first measurement that the device takes in auto-range mode is a 10-ms range assessment measurement. The device then determines the appropriate full-scale range to take its first full measurement.

For subsequent measurements, the full-scale range is set by the result of the previous measurement. If a measurement is towards the low side of full-scale, then the full-scale range is decreased by one or two settings for the next measurement. If a measurement is towards the upper side of full-scale, then the full-scale range is increased by one setting for the next measurement.

If the measurement exceeds the full-scale range, resulting from a fast-increasing optical transient event, then the current measurement is aborted. This invalid measurement is not reported. A 10-ms measurement is taken to assess and properly reset the full-scale range. Then, a new measurement is taken with this proper full-scale range. Therefore, during a fast-increasing optical transient in this mode, a measurement can possibly take longer to complete and report than indicated by the configuration register conversion time field (CT).

7.4.2 Interrupt Reporting Mechanism Modes

There are two major types of interrupt reporting mechanism modes: latched window-style comparison mode and transparent hysteresis-style comparison mode. The configuration register latch field (L) (see the configuration register, bit 4) controls which of these two modes is used. An end-of-conversion mode is also associated with each major mode type. The end-of-conversion mode is active when the two most significant bits of the threshold low register are set to 11b. The mechanisms report via the flag high and flag low fields, the conversion ready field, and the INT pin.

7.5.1 Writing and Reading

Accessing a specific register on the OPT3002 is accomplished by writing the appropriate register address during the I²C transaction sequence. See Table 6 for a complete list of registers and the corresponding register addresses. The value for the register address (as shown in Figure 15) is the first byte transferred after the slave address byte with the R/W bit low.

1.

NOINDENT:

The value of the slave address byte is determined by the ADDR pin setting; see Table 1.

Figure 15. Setting the I²C Register Address Timing Diagram

Writing to a register begins with the first byte transmitted by the master. This byte is the slave address with the R/W bit low. The OPT3002 then acknowledges receipt of a valid address. The next byte transmitted by the master is the address of the register that data are to be written to. The next two bytes are written to the register addressed by the register address. The OPT3002 acknowledges receipt of each data byte. The master can terminate the data transfer by generating a start or stop condition.

When reading from the OPT3002, the last value stored in the register address by a write operation determines which register is read during a read operation. To change the register address for a read operation, a new partial I²C write transaction must be initiated. This partial write is accomplished by issuing a slave address byte with the R/W bit low, followed by the register address byte and a stop command. The master then generates a start condition and sends the slave address byte with the R/W bit high to initiate the read command. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the register address. This byte is followed by an acknowledge from the master; then the slave transmits the least significant byte. The master acknowledges receipt of the data byte. The master can terminate the data transfer by generating a not-acknowledge after receiving any data byte, or by generating a start or stop condition. If repeated reads from the same register are desired, continually sending the register address bytes is not necessary; the OPT3002 retains the register address until that number is changed by the next write operation.

Figure 16 and Figure 17 show the write and read operation timing diagrams, respectively. Note that register bytes are sent most significant byte first, followed by the least significant byte.

1.

NOINDENT:

The value of the slave address byte is determined by the setting of the ADDR pin; see Table 1.

Figure 16. I²C Write Example Timing Diagram

1.

NOINDENT:

The value of the slave address byte is determined by the ADDR pin setting; see Table 1.

2.

NOINDENT:

An ACK by the master can also be sent.

Figure 17. I²C Read Example Timing Diagram

7.5.1.3 SMBus Alert Response

The SMBus alert response provides a quick identification for which device issued the interrupt. Without this alert response capability, the processor does not know which device pulled the interrupt line when there are multiple slave devices connected.

The OPT3002 is designed to respond to the SMBus alert response address, when in the latched window-style comparison mode (configuration register, latch field = 1). The OPT3002 does not respond to the SMBus alert response when in transparent mode (configuration register, latch field = 0).

The response behavior of the OPT3002 to the SMBus alert response is shown in Figure 18. When the interrupt line to the processor is pulled to active, the master can broadcast the alert response slave address (0001 1001b). Following this alert response, any slave devices that generated an alert identify themselves by acknowledging the alert response and sending their respective I²C address on the bus. The alert response can activate several different slave devices simultaneously. If more than one slave attempts to respond, bus arbitration rules apply. The device with the lowest address wins the arbitration. If the OPT3002 loses the arbitration, then the device does not acknowledge the I²C transaction and its INT pin remains in an active state, prompting the I²C master processor to issue a subsequent SMBus alert response. When the OPT3002 wins the arbitration, the device acknowledges the transaction and sets its INT pin to inactive. The master can issue that same command again, as many times as necessary to clear the INT pin. See the Interrupt Reporting Mechanism Modes section for additional details of how the flags and INT pin are controlled. The master can obtain information about the source of the OPT3002 interrupt from the address broadcast in the above process. The flag high field (configuration register, bit 6) is sent as the final LSB of the address to provide the master additional information about the cause of the OPT3002 interrupt. If the master requires additional information, then the result register or the configuration register can be queried. The flag high and flag low fields are not cleared upon an SMBus alert response.

1.

NOINDENT:

FH is the flag high field (FH) in the configuration register (see Table 10).

2.

NOINDENT:

A1 and A0 are determined by the ADDR pin; see Table 1.

Figure 18. SMBus Alert Response Timing Diagram

7.6.1 Internal Registers

The device is operated over the I²C bus with registers that contain configuration, status, and result information. All registers are 16 bits long.

There are four main registers: result, configuration, low-limit, and high-limit. There is also a manufacturer ID register. Table 6 lists these registers. Do not write or read registers that are not shown on this register map.