JAJSOP2 データシート

JAJSOP2 December 2022 OPT3005

PRODUCTION DATA

7.6 Timing Requirements

see note ⁽¹⁾

		MIN	NOM	MAX	UNIT
I²C FAST MODE
f_SCL	SCL operating frequency	0.01		0.4	MHz
t_BUF	Bus free time between stop and start	1300			ns
t_HDSTA	Hold time after repeated start	600			ns
t_SUSTA	Setup time for repeated start	600			ns
t_SUSTO	Setup time for stop	600			ns
t_HDDAT	Data hold time	20		900	ns
t_SUDAT	Data setup time	100			ns
t_LOW	SCL clock low period	1300			ns
t_HIGH	SCL clock high period	600			ns
t_RC and t_FC	Clock rise and fall time			300	ns
t_RD and t_FD	Data rise and fall time			300	ns
t_TIMEO	Bus timeout period. If the SCL line is held low for this duration of time, the bus state machine is reset.		28		ms
I²C HIGH-SPEED MODE
f_SCL	SCL operating frequency	0.01		2.6	MHz
t_BUF	Bus free time between stop and start	160			ns
t_HDSTA	Hold time after repeated start	160			ns
t_SUSTA	Setup time for repeated start	160			ns
t_SUSTO	Setup time for stop	160			ns
t_HDDAT	Data hold time	20		140	ns
t_SUDAT	Data setup time	20			ns
t_LOW	SCL clock low period	240			ns
t_HIGH	SCL clock high period	60			ns
t_RC and t_FC	Clock rise and fall time			40	ns
t_RD and t_FD	Data rise and fall time			80	ns
t_TIMEO	Bus timeout period. If the SCL line is held low for this duration of time, the bus state machine is reset.		28		ms

(1) All timing parameters are referenced to low and high voltage thresholds of 30% and 70%, respectively, of final settled value.

Figure 7-1 I²C Detailed Timing Diagram