JAJSO51 May   2022 PCM1822

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: TDM or I2S Interface
    7. 7.7 Switching Characteristics: TDM or I2S Interface
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hardware Control
      2. 8.3.2 Audio Serial Interfaces
        1. 8.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 8.3.2.2 Inter IC Sound (I2S) Interface
      3. 8.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 8.3.4 Input Channel Configurations
      5. 8.3.5 Reference Voltage
      6. 8.3.6 Signal-Chain Processing
        1. 8.3.6.1 Digital High-Pass Filter
        2. 8.3.6.2 Configurable Digital Decimation Filters
          1. 8.3.6.2.1 Linear Phase Filters
            1. 8.3.6.2.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 8.3.6.2.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 8.3.6.2.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 8.3.6.2.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 8.3.6.2.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 8.3.6.2.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 8.3.6.2.1.7 Sampling Rate: 192 kHz or 176.4 kHz
          2. 8.3.6.2.2 Low-Latency Filters
            1. 8.3.6.2.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.6.2.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.6.2.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.6.2.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.6.2.2.5 Sampling Rate: 96 kHz or 88.2 kHz
      7. 8.3.7 Dynamic Range Enhancer (DRE)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.8 Typical Characteristics

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode, PLL on, DRE_LVL = –36 dB, channel gain = 0 dB, and linear phase decimation filter (unless otherwise noted); all performance measurements are done with a 20-kHz, low-pass filter, and an A-weighted filter

Figure 7-1 Differential Input: THD+N vs Input Amplitude
With DRE Enabled
Figure 7-3 Differential Input: DR vs Input Frequency
With DRE Enabled
Figure 7-5 Differential Input: THD+N vs Input Frequency
With a –1-dBr Input
Figure 7-7 Power-Supply Rejection Ratio vs
Ripple Frequency With a 100-mVPP Amplitude
Figure 7-9 Differential Input: FFT With Idle Input and DRE Disabled
Figure 7-11 Differential Input: FFT With a –60-dBr Input and DRE Disabled
Figure 7-13 Single-Ended Input: THD+N vs Input Amplitude
With DRE Disabled
Figure 7-15 Single-Ended Input: DR vs Input Frequency
With DRE Disabled
Figure 7-17 Single-ended Input: Frequency Response
With a –12-dBr Input
Figure 7-19 Single-ended Input: FFT With Idle Input and DRE Disabled
Figure 7-21 Single-ended Input: FFT With a –60-dBr Input and DRE Disabled
Figure 7-2 Differential Input: THD+N vs Input Amplitude
With DRE Disabled
Figure 7-4 Differential Input: DR vs Input Frequency
With DRE Disabled
Figure 7-6 Differential Input: Frequency Response
With a –12-dBr Input
Figure 7-8 Differential Input: FFT With Idle Input and DRE Enabled
Figure 7-10 Differential Input: FFT With a –60-dBr Input and DRE Enabled
Figure 7-12 Differential Input: FFT With a –1-dBr Input
Figure 7-14 Single-ended Input: DR vs Input Frequency
With DRE Enabled
Figure 7-16 Single-Ended Input: THD+N vs Input Frequency
With a –1-dBr Input
Figure 7-18 Single-ended Input: FFT With Idle Input and DRE Enabled
Figure 7-20 Single-ended Input: FFT With a –60-dBr Input and DRE Enabled
Figure 7-22 Single-ended Input: FFT With a –1-dBr Input