JAJSUM7 May   2024 PCM1841-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 5.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 5.8 Timing Diagram
    9. 5.9 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Hardware Control
      2. 6.3.2 Audio Serial Interfaces
        1. 6.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 6.3.2.2 Inter IC Sound (I2S) Interface
        3. 6.3.2.3 Left-Justified (LJ) Interface
      3. 6.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 6.3.4 Input Channel Configurations
      5. 6.3.5 Reference Voltage
      6. 6.3.6 Microphone Bias
      7. 6.3.7 Signal-Chain Processing
        1. 6.3.7.1 Digital High-Pass Filter
        2. 6.3.7.2 Configurable Digital Decimation Filters
          1. 6.3.7.2.1 Linear Phase Filters
            1. 6.3.7.2.1.1 Sampling Rate: 8kHz or 7.35kHz
            2. 6.3.7.2.1.2 Sampling Rate: 16kHz or 14.7kHz
            3. 6.3.7.2.1.3 Sampling Rate: 24kHz or 22.05kHz
            4. 6.3.7.2.1.4 Sampling Rate: 32kHz or 29.4kHz
            5. 6.3.7.2.1.5 Sampling Rate: 48kHz or 44.1kHz
            6. 6.3.7.2.1.6 Sampling Rate: 96kHz or 88.2kHz
            7. 6.3.7.2.1.7 Sampling Rate: 192kHz or 176.4kHz
          2. 6.3.7.2.2 Low-Latency Filters
            1. 6.3.7.2.2.1 Sampling Rate: 16kHz or 14.7kHz
            2. 6.3.7.2.2.2 Sampling Rate: 24kHz or 22.05kHz
            3. 6.3.7.2.2.3 Sampling Rate: 32kHz or 29.4kHz
            4. 6.3.7.2.2.4 Sampling Rate: 48kHz or 44.1kHz
            5. 6.3.7.2.2.5 Sampling Rate: 96kHz or 88.2kHz
      8. 6.3.8 Dynamic Range Enhancer (DRE)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Hardware Shutdown
      2. 6.4.2 Active Mode
  8. 7Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9Revision History
  11.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

PCM1841-Q1 RGE Package,24-Pin VQFN With Exposed Thermal Pad,Top View Figure 4-1 RGE Package,24-Pin VQFN With Exposed Thermal Pad,Top View
Table 4-1 Pin Functions
PIN TYPE (1) DESCRIPTION
NO. NAME
1 AVDD P Analog power (3.3V, nominal)
2 AREG P Analog on-chip regulator output voltage for analog supply (1.8V, nominal)
3 VREF O Analog reference voltage filter output
4 AVSS GND Analog ground. Short this pin directly to the board ground plane.
5 MICBIAS O MICBIAS output
6 IN1P I Analog input 1P pin
7 IN1M I Analog input 1M pin
8 IN2P I Analog input 2P pin
9 IN2M I Analog input 2M pin
10 IN3P I Analog input 3P pin
11 IN3M I Analog input 3M pin
12 IN4P I Analog input 4P pin
13 IN4M I Analog input 4M pin
14 SHDNZ I Digital input. Device hardware shutdown and reset (active low)
15 FMT1 I Digital input. Audio interface format select 1 pin
16 FMT0 I Digital input. Audio interface format select 0 pin
17 MSZ I Digital input. Audio interface bus controller or target select pin
18 MD0 I Digital input. Device configuration mode select 0 pin
19 IOVDD P Digital I/O power supply (1.8V or 3.3V, nominal)
20 MD1 I Digital input. Device configuration mode select 1 pin
21 SDOUT O Digital output. Audio serial data interface bus output
22 BCLK I/O Audio serial data interface bus bit clock
23 FSYNC I/O Audio serial data interface bus frame synchronization signal
24 DREG P Digital regulator output voltage for digital core supply (1.5V, nominal)
A1, A2,A3,A4 AVSS GND Analog ground. Short this pin directly to the board ground plane.
Thermal Pad (VSS) GND Thermal pad shorted to internal device ground. Short thermal pad directly to board ground plane.
(1) I = input, O = output, P = power, FB = feedback, GND = ground, N/A = not applicable