JAJSUM7 May   2024 PCM1841-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 5.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 5.8 Timing Diagram
    9. 5.9 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Hardware Control
      2. 6.3.2 Audio Serial Interfaces
        1. 6.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 6.3.2.2 Inter IC Sound (I2S) Interface
        3. 6.3.2.3 Left-Justified (LJ) Interface
      3. 6.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 6.3.4 Input Channel Configurations
      5. 6.3.5 Reference Voltage
      6. 6.3.6 Microphone Bias
      7. 6.3.7 Signal-Chain Processing
        1. 6.3.7.1 Digital High-Pass Filter
        2. 6.3.7.2 Configurable Digital Decimation Filters
          1. 6.3.7.2.1 Linear Phase Filters
            1. 6.3.7.2.1.1 Sampling Rate: 8kHz or 7.35kHz
            2. 6.3.7.2.1.2 Sampling Rate: 16kHz or 14.7kHz
            3. 6.3.7.2.1.3 Sampling Rate: 24kHz or 22.05kHz
            4. 6.3.7.2.1.4 Sampling Rate: 32kHz or 29.4kHz
            5. 6.3.7.2.1.5 Sampling Rate: 48kHz or 44.1kHz
            6. 6.3.7.2.1.6 Sampling Rate: 96kHz or 88.2kHz
            7. 6.3.7.2.1.7 Sampling Rate: 192kHz or 176.4kHz
          2. 6.3.7.2.2 Low-Latency Filters
            1. 6.3.7.2.2.1 Sampling Rate: 16kHz or 14.7kHz
            2. 6.3.7.2.2.2 Sampling Rate: 24kHz or 22.05kHz
            3. 6.3.7.2.2.3 Sampling Rate: 32kHz or 29.4kHz
            4. 6.3.7.2.2.4 Sampling Rate: 48kHz or 44.1kHz
            5. 6.3.7.2.2.5 Sampling Rate: 96kHz or 88.2kHz
      8. 6.3.8 Dynamic Range Enhancer (DRE)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Hardware Shutdown
      2. 6.4.2 Active Mode
  8. 7Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9Revision History
  11.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

at TA = 25°C, AVDD = 3.3V, IOVDD = 3.3V, fIN = 1kHz sinusoidal signal, fS = 48kHz, 32 bit audio data, BCLK = 256 × fS, TDM target mode (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC CONFIGURATION
AC input impedance Input pins INxP or INxM 2.5 kΩ
ADC PERFORMANCE FOR LINE/MICROPHONE INPUT RECORDING : AVDD 3.3V OPERATION
Differential input full-scale AC signal voltage AC-coupled input 2 VRMS
SNR Signal-to-noise ratio, A-weighted(1)(2) IN1 differential input selected and AC signal shorted to ground, DRE enabled (DRE_LVL = –36dB, DRE_MAXGAIN = 24dB) 115 122 dB
IN1 differential input selected and AC signal shorted to ground, DRE disabled 106 112
DR Dynamic range, A-weighted(2) IN1 differential input selected and –60dB full-scale AC signal input, DRE enabled (DRE_LVL = –36dB, DRE_MAXGAIN = 24dB) 123 dB
IN1 differential input selected and –60dB full-scale AC signal input, DRE disabled 113
THD+N Total harmonic distortion(2)(3) IN1 differential input selected and –1dB full-scale AC signal input, DRE enabled (DRE_LVL = –36dB, DRE_MAXGAIN = 24dB) –98 –80 dB
IN1 differential input selected and –1dB full-scale AC signal input, DRE disabled –98
ADC OTHER PARAMETERS
Output data sample rate 7.35 192 kHz
Output data sample word length 32 Bits
Interchannel isolation –1dB full-scale AC-signal input to non measurement channel –124 dB
Interchannel gain mismatch –6dB full-scale AC-signal input 0.1 dB
Gain drift across temperature range 15°C to 35°C –4.4 ppm/°C
Interchannel phase mismatch 1kHz sinusoidal signal 0.02 Degrees
Phase drift 1kHz sinusoidal signal, across temperature range 15°C to 35°C 0.0005 Degrees/°C
PSRR Power-supply rejection ratio 100mVPP, 1kHz sinusoidal signal on AVDD, differential input selected, 0dB channel gain 102 dB
CMRR Common-mode rejection ratio Differential microphone input selected, 100mVPP, 1kHz signal on both pins and measure level at output 60 dB
MICROPHONE BIAS
MICBIAS noise BW = 20Hz to 20kHz, A-weighted, 1μF capacitor between MICBIAS and AVSS 1.6 µVRMS
MICBIAS voltage VREF V
MICBIAS current drive 20 mA
MICBIAS load regulation Measured up to max load 0 0.6 1.8 %
MICBIAS over current protection threshold 22 mA
DIGITAL I/O
VIL(SHDNZ) Low-level digital input logic voltage threshold SHDNZ pin –0.3 0.25 × IOVDD V
VIH(SHDNZ) High-level digital input logic voltage threshold SHDNZ pin 0.75 × IOVDD IOVDD + 0.3 V
VIL Low-level digital input logic voltage threshold All digital pins, IOVDD 1.8V operation –0.3 0.3 × IOVDD V
All digital pins, IOVDD 3.3V operation –0.3 0.8
VIH High-level digital input logic voltage threshold All digital pins, IOVDD 1.8V or 3.3V operation 0.7 × IOVDD IOVDD + 0.3 V
VOL Low-level digital output voltage All digital pins, IOL = –2mA, IOVDD 1.8V operation 0.45 V
All digital pins, IOL = –2mA, IOVDD 3.3V operation 0.4
VOH High-level digital output voltage All digital pins, IOH = 2mA, IOVDD 1.8V operation IOVDD – 0.45 V
All digital pins, IOH = 2mA, IOVDD 3.3V operation 2.4
IIH Input logic-high leakage for digital inputs All digital pins, input = IOVDD –5 0.1 5 µA
IIL Input logic-low leakage for digital inputs All digital pins, input = 0V –5 0.1 5 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD Current consumption in hardware shutdown mode SHDNZ = 0, AVDD = 3.3V, internal AREG 1 µA
IIOVDD SHDNZ = 0, all external clocks stopped, IOVDD = 3.3V 0.2
IIOVDD SHDNZ = 0, all external clocks stopped, IOVDD = 1.8V 0.15
IAVDD Current consumption with ADC 4 channel operating at fS 16kHz, BCLK = 256 × fS and DRE disable AVDD = 3.3V, internal AREG 21.3 mA
IIOVDD IOVDD = 3.3V 0.15
IIOVDD IOVDD = 1.8V 0.04
IAVDD Current consumption with ADC 4 channel operating at fS 48kHz, BCLK = 256 × fS and DRE disable AVDD = 3.3V, internal AREG 22.9 mA
IIOVDD IOVDD = 3.3V 0.25
IIOVDD IOVDD = 1.8V 0.1
IAVDD Current consumption with ADC 4 channel operating at fS 48kHz, BCLK = 256 × fS and DRE enable  AVDD = 3.3V, internal AREG 25.0 mA
IIOVDD IOVDD = 3.3V 0.25
IIOVDD IOVDD = 1.8V 0.1
(1) Ratio of output level with 1kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A-weighted over a 20Hz to 20kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) For best distortion performance, use input AC-coupling capacitors with low-voltage-coefficient.