JAJSF44D March 2014 – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865
PRODUCTION DATA.
CLK_DIV_SCK_BCK is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | DIVNUM | ||||||
R/W-0b | R/W-000 0011b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RSV | R/W | 0 | Reserved. Do not access. |
6-0 | DIV_NUM | R/W | 000 0011b | Set Master Clock (SCK) to BCK Divider Value
Ratio of master clock (SCK) to bit clock (BCK) in master mode Divider value: 0: 1 1: 1/2 2: 1/3 3: 1/4 (default) : 7: 1/8 : 127: 1/128 |