JAJSF44 データシート

10.3.9.5 Software-Controlled Devices Manual PLL Calculation

The PCM186x has an on-chip PLL with fractional multiplication to generate the clock frequency required by the audio ADC, modulator and digital signal processing blocks. The programmability of the PLL allows operation from a wide variety of clocks that may be available in the system. The PLL input supports clocks varying from 1 MHz to 50 MHz, and is register programmable to enable generation of required sampling rates with fine precision.

The PLL by default is enabled because the on-chip fixed function DSPs require high clock rates to complete all various decimation, mixing, and level-detection functions. The PLL output clock PLLCK is given by Equation 1:

Equation 1. PCM1860 PCM1861 PCM1862 PCM1863 PCM1864 PCM1865 EQ1_PLLCK_las831.gif

where

R = 1, 2, 3, 4, ….. 15, 16
J = 1, 2, 3, 4,...63, and D = 0000, 0001, 0002...9999
K = J.D
P = 1, 2, 3...15

R, J, D, and P are register programmable. J is the integer portion of K (the numbers to the left of the decimal point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).

Examples:

If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000 (that is, an integer multiple), the following conditions must be satisfied:

1 MHz ≤ (PLLCKIN / P) ≤ 20 MHz
64 MHz < (PLLCKIN × K × R / P) < 100 MHz
1 ≤ J ≤ 63

When the PLL is enabled and D ≠ 0000 (that is, a noninteger multiple), the following conditions must be satisfied:

6.667 MHz ≤ (PLLCLKIN / P) ≤ 20 MHz
64 MHz < (PLLCKIN x K x R / P) < 100 MHz
4 ≤ J ≤ 11
R = 1

When the PLL is enabled,

f_Sref = (PLLCLKIN × K × R) / (N × P) :
N is selected so that f_Sref × N = PLLCLKIN × K × R / P is in the allowable range.

Example:

MCLK = 12 MHz and f_Sref = 44.1 kHz, (N=2048)
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example:

MCLK = 12 MHz and f_Sref = 48.0 kHz, (N=2048)
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

The PLL can be programmed using page 0, registers 0x28 thru 0x2D. Turn on the PLL using page 0, register 0x28, D(0). The variable P can be programmed using page 0, register 0x29, D(3:0). The variable R can be programmed using page 0, register 0x2A, D(3:0). The variable J can be programmed using page 0, register 0x2B, D(5:0). The variable D is 14-bits and is programmed into two registers. The MSB portion is programmed using page 0, register 0x2D, D(5:0), and the LSB portion is programmed using page 0, register 0x2C, D(7:0). The variable D is set when the LSB portion is programmed.

Values are programmed in the registers in Table 14.

Table 14. PLL Coefficient Registers

REGISTER	FUNCTION	BITS
PLL_EN	PLL enable, lock status and PLL reference	Page 0, register 0x28
PLL_P	PLL P	Page 0, register 0x29
PLL_J	PLL J	Page 0, register 0x2B
PLL_Dx	PLL D	Page 0, register 0x2C (least significant bits)
PLL_Dx	PLL D	Page 0, register 0x2D (most significant bits)
PLL_R	PLL R	Page 0, register 0x2A

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10.3.9.5 Software-Controlled Devices Manual PLL Calculation

Table 14. PLL Coefficient Registers