JAJSF44D March 2014 – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865
PRODUCTION DATA.
The PCM186x has a clock error detection block inside that continues to monitor the ratio of BCK to LRCK.
If a clock error is detected (such as an unexpected number of BCKs per LRCK), then the device goes into standby mode.
If all the clocks are stopped going into the device, then the device shifts into sleep state, and begins Energysense signal detect mode.
When a clock error occurs, the PCM186x starts the following sequence:
If the device stops transmitting data, the first step is to read CLK_ERR_STAT (Page.0 0x72). The least significant nibble shows the device status. Value 0x01 suggests Clock Waiting State, at which point the clock error status can be read in register STATE (Page.0 0x75). The clock detection logic is shown in Table 15.
SCK | BCK | LRCK | RESULT | ACTION |
---|---|---|---|---|
ACTIVE | ACTIVE | ACTIVE | No error | Normal operation |
ACTIVE | ACTIVE | HALT | Clock error | Enter clock waiting state |
ACTIVE | HALT | ACTIVE | Clock error | Enter clock waiting state |
ACTIVE | HALT | HALT | Clock error | Enter SLEEP |
HALT | ACTIVE | ACTIVE | No error | Enter BCK PLL mode |
HALT | ACTIVE | HALT | Clock error | Enter clock waiting state |
HALT | HALT | ACTIVE | Clock error | Enter clock waiting state |
HALT | HALT | HALT | Clock error | Enter SLEEP |
In addition, the device uses an on-chip oscillator to detect errors in the rate of present clocks. That logic is shown in Table 16.
SCK/LRCK Ratio | BCK/LRCK RATIO | LRCK | ERROR DETECT | ACTION |
---|---|---|---|---|
- | - | < 8 kHz or > 192 kHz | fS error | Enter clock waiting state |
Not 128 / 256 / 384 / 512 / 768 | - | 8 / 16 / 32 / 44.1 / 48 kHz | SCK error | Enter the clock waiting state, tie I2S output to 0 |
Not 128 / 256 / 384 / 512 | - | 88.2 / 96 kHz | SCK error | Enter the clock waiting state, tie I2S output to 0 |
Not 128 / 256 | - | 176.4 / 192 kHz | SCK error | Enter the clock waiting state, tie I2S output to 0 |
Not 256 / 64 / 48 / 32 | 8 / 16 / 32 / 44.1 / 48 / 88.2 / 96 / 174.6 / 196 kHz | BCK error | Enter the clock waiting state, tie I2S output to 0 | |
>192 kHz | fS error | Enter the clock waiting state, tie I2S output to 0 |
In an application with a non-audio standard SCK coming into the product, the clock error detection on the SCK pin can be ignored by disabling the auto clock detector (CLKDET_EN Page.0 0x20).