JAJSF44D March 2014 – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865
PRODUCTION DATA.
CLK_DIV_BCK_LRCK is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV_NUM | |||||||
R/W-0011 1111b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIV_NUM | R/W | 0011 1111b | Set Bit Clock (BCK) to LRCK Divider Value
Ratio of bit clock (BCK) to word clock (LRCK) in master mode Divider value: 0: 1 1: 1/2 2: 1/3 3: 1/4 : 63: 1/64 (default) : 127: 1/128 : 255: 1/256 |