JAJSF44D March 2014 – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865
PRODUCTION DATA.
AUXADC_DATA_CTRL is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DC_NOLATCH | AUXADC_RDY | DC_RDY | AUXADC_LATCH | AUXADC_DATA_TYPE | DC_CH | ||
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DC_NOLATCH | R/W | 0b | Read Without Latch
Read directly without latch operation (from secondary ADC) 0: With latch operation (default) 1: Without latch operation when read dc value |
6 | AUXADC_RDY | R/W | 0b | AUXADC Ready
Indicate latch operation is finished and AUXADC value is ready for read operation. 0: Latch operation is running (default) 1: AUXADC value is ready for read operation |
5 | DC_RDY | R/W | 0b | DC Ready
Indicate latch operation is finished and dc value is ready. 0: Latch operation is running (default) 1: DC value is ready for read operation |
4 | AUXADC_LATCH | R/W | 0b | AUXADC Latch
Trigger to latch 16-bit AUXADC value for read operation: rising edge is the trigger signal 0: Idle (default) 1: Latch the value for read operation |
3 | AUXADC_DATA_TYPE | R/W | 0b | Data to be Read From Control Interface
0: read LPF data (default) 1: read HPF data |
2-0 | DC_CH[2:0] | R/W | 000b | DC-Value Channel Select
Select dc-value channel to be latched for control-interface read operation 000: CH1_L (default) 001: CH1_R 010: CH2_L 011: CH2_R 100: CH3_L 101: CH3_R 110: CH4_L 111: CH4_R |