JAJSF44D March 2014 – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POL | RSV | SEL_L | |||||
R/W-0b | R/W-1b | R/W-00 0001b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | POL | R/W | 0b |
Change ADC1_INPUT_SEL_L Signal Polarity 0: Normal (default) 1: Inverted |
6 | RSV | R/W | 1b | Reserved. Always write 1. |
5-0 | SEL_L | R/W | 00 0001b | ADC 1 Input Channel Select (ADC1L)
00 0000: No select 00 0001: VINL1[SE] (default) 00 0010: VINL2[SE] 00 0011: VINL2[SE] + VINL1[SE] 00 0100: VINL3[SE] 00 0101: VINL3[SE] + VINL1[SE] 00 0110: VINL3[SE] + VINL2[SE] 00 0111: VINL3[SE] + VINL2[SE] + VINL1[SE] 00 1000: VINL4[SE] 00 1001: VINL4[SE] + VINL1[SE] 00 1010: VINL4[SE] + VINL2[SE] 00 1011: VINL4[SE] + VINL2[SE] + VINL1[SE] 00 1100: VINL4[SE] + VINL3[SE] 00 1101: VINL4[SE] + VINL3[SE] + VINL1[SE] 00 1110: VINL4[SE] + VINL3[SE] + VINL2[SE] 00 1111: VINL4[SE] + VINL3[SE] + VINL2[SE] + VINL1[SE] 01 0000: {VIN1P, VIN1M}[DIFF] 10 0000: {VIN4P, VIN4M}[DIFF] 11 0000: {VIN1P, VIN1M}[DIFF] + {VIN4P, VIN4M}[DIFF] |