12.1.1 Power-Supply Pins (VCCAD1/2, VCCDA1/2, and VDD1/2)

The digital and analog power-supply pins of the PCM3168A device should be bypassed to the corresponding ground pins with 1-μF ceramic capacitors placed as close to the pins as possible. Each power-supply line (V_CC and V_DD) to the PCM3168A device should be bypassed to the corresponding ground pins with 10-μF electrolytic capacitors to maximize the dynamic performance of the ADC and DAC.

Although the PCM3168A device has two power lines to maximize the potential of dynamic performance, using one common source (for instance, a 5-V power supply for V_CC and a 3.3-V power supply for V_DD generated from one common source) is recommended to avoid unexpected power-supply trouble such as latch-up or incorrect power-supply conditions. Also, simultaneous power-on/off of V_CC and V_DD is recommended to avoid unexpected transient responses in outputs, though the power-supply sequence of V_CC and V_DD is not specified in the operation and absolute maximum ratings point of view.

12.1.2 Grounding (AGNDAD1/2, AGNDDA1/2, and DGND1/2)

To maximize the dynamic performance of the PCM3168A device, the analog and digital grounds are not connected internally. These pins should have very low impedances to avoid digital noise and signal components feeding back into the analog ground. All ground pins should be connected directly to each other under the part, and the device should be connected to the analog ground of the application, as with acceptable analog layout practices; this layout reduces the potential of noise problems.

12.1.3 VIN1±, VIN2±, VIN3±, VIN4±, VIN5±, and VIN6± Pins

In case of direct interface to VINx±, 1-μF electrolytic capacitors are recommended because the ac-coupling capacitor (which gives a 2-Hz HPF corner frequency and 47-Ω and 0.1-μF to 470-Ω and 0.001-μF differential LPF) is recommended as the anti-aliasing filter that gives a 160-kHz LPF corner frequency. If signal source impedance is not enough (too low) or input line length to the VINx± is not enough (too short), insertion of an analog front-end buffer (see Figure 58 to Figure 60) is recommended to maximize the dynamic performance. The voltage coefficient of the capacitor for an anti-aliasing filter should be considered to maximize the THD performance. A film-type capacitor is recommended; if a ceramic capacitor is used, a relatively higher voltage type is recommended.

There are three ways to terminate any unused input pins. First, terminate these pins to AGNDAD with 0.001-μF to 1-μF capacitors. This termination is applied on unused pins whose channels are configured in single-ended mode. The second form of termination is to connect the positive (+) pin and negative (–) pins together and terminating these to AGNDAD with 0.001-μF to 1-μF capacitors. This option applies to unused pins with channels that are configured in differential mode. The last termination method is to terminate the pins directly to VCOMAD; this option can be applied on unused pins with unused channels combined into two channels that are then configured in power-save mode.

12.1.4 VCOMAD and VCOMDA Pins

10-μF electrolytic capacitors are recommended between VCOMAD and AGNDAD, and VCOMDA and AGNDDA to ensure a low source impedance of ADC and DAC common voltages. These capacitors should be located as close to each pin as possible to reduce dynamic errors on the ADC and DAC common voltages.

12.1.5 VREFAD1/2 Pins

10-μF electrolytic capacitors are recommended between VREFAD1/2 and AGNDAD to ensure low source impedances of ADC references. These capacitors should be located as close to each pin as possible to reduce dynamic errors on ADC references.

12.1.6 VOUT1±, VOU2±, VOUT3±, VOUT4±, VOUT5±, VOUT6±, VOUT7±, and VOUT8± Pins

The differential to single-ended buffer with post LPF can be directly connected (without capacitors) to these output pins (see Figure 62), thereby minimizing the use of coupling capacitors for the 2-V_RMS outputs. The op amp and resistors must be determined with consideration of degrading some performance through this differential to single-ended and LPF buffer; there is about 1.5-dB degradation seen in the examples of Figure 61 and Figure 62.

12.1.7 MODE Pin

This pin is a logic input with quad-state input capability. The MODE pin is high when connected to V_DD, low when connected to DGND, and pulled up or pulled down through an external resistor and for the two mid-states in order to distinguish the four input states. The pull-up or pull-down resistor must be 220 kΩ, ±5% in tolerance. Note that the state of the MODE pin is only sampled by a power-on or a low-to-high transition of the RST pin.

12.1.8 RST Pin

When the MODE pin setting changes to change the operating mode, the new mode setting does not take effect immediately; a RST pin toggle is required to make the new mode setting valid, and for the new mode to take effect.

12.1.9 OVF Pin

The OVF pin has two functions. It is primarily the flag for ADC overflow occurrence detection. It is also used to indicate that the internal reset sequence is complete and that the device is ready to enter serial mode control.

12.1.10 System Clock and Audio Interface Clocks

The quality of SCKI may influence dynamic performance, because the PCM3168A device (both the ADC and DAC) operates based on SCKI. Therefore, it may be required to consider the jitter, duty, and rise and fall time of the system clock.

In slave mode, the PCM3168A device does not require a specific timing relationship between BCKAD/LRCKAD and SCKI, and BCKDA/LRCKDA and SCKI; however, there is a possibility of performance degradation with a certain timing relationship between them. In that case, specific timing relationship control might resolve this performance degradation.

In master mode, there is a possibility of performance degradation because of heavy loads on BCKAD/LRCKAD, BCKDA/LRCKDA, and DOUT1/2/3. It is recommended to load these pins as lightly as possible. Note that all output clocks and signals go low; they do not go into a high-impedance state during power-save mode.

12.1.11 PowerPAD

The PowerPAD of the PCM3168A device is internally connected to the substrate of the silicon. It should be connected to the ground plane with sufficient low conductance in electrical and thermal; see Figure 54. The PowerPAD size is 7.25 mm x 7.00 mm (0.725 cm × 0.7 cm).

12.1.12 External Mute Control

For power-down ON/OFF control without the pop-noise that is generated by a DC level change on the DAC output, the external mute control is generally required. Use of the following control sequence is recommended: external mute ON, codec power-down ON, SCKI stop and resume if necessary, codec power-down OFF, and external mute OFF control.