SLAS859C May   2012  – May 2015 PCM5100A , PCM5100A-Q1 , PCM5101A , PCM5101A-Q1 , PCM5102A , PCM5102A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified System Diagram
  5. 5 Revision History
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings Updated ESD Data
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Timing Requirements, XSMT
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Terminology
      2. 9.3.2 Audio Data Interface
        1. 9.3.2.1 Audio Serial Interface
        2. 9.3.2.2 PCM Audio Data Formats
        3. 9.3.2.3 Zero Data Detect
      3. 9.3.3 XSMT Pin (Soft Mute / Soft Un-Mute)
      4. 9.3.4 Audio Processing
        1. 9.3.4.1 Interpolation Filter
      5. 9.3.5 Reset and System Clock Functions
        1. 9.3.5.1 Clocking Overview
        2. 9.3.5.2 Clock Slave Mode With Master/System Clock (SCK) Input (4 Wire I2S)
        3. 9.3.5.3 Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM)
    4. 9.4 Device Functional Modes
      1. 9.4.1 External SCK and PLL Activation
        1. 9.4.1.1 Interpolation Filter Modes
        2. 9.4.1.2 44.1kHz De-emphasis
        3. 9.4.1.3 Audio Format
  10. 10Applications and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Typical Applications
        1. 10.1.1.1 Example Design Requirements
        2. 10.1.1.2 Detailed Design Procedure
        3. 10.1.1.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Distribution and Requirements
    2. 11.2 Recommended Powerdown Sequence
      1. 11.2.1 Planned Shutdown
      2. 11.2.2 Unplanned Shutdown
    3. 11.3 External Power Sense Undervoltage Protection Mode
    4. 11.4 Power-On Reset Function
    5. 11.5 PCM510xA Power Modes
      1. 11.5.1 Setting Digital Power Supplies and I/O Voltage Rails
      2. 11.5.2 Power Save Modes
  12. 12Layout
    1. 12.1 Layout Guidelines
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Revision History

Changes from B Revision (January 2015) to C Revision

  • Changed the device number from "PCM510x" to "PCM510xA" in the Simplified System DiagramGo
  • Changed typical performance table to reflect part differences accurately Go
  • Changed "Storage temperatures, Tstg" to "Operating junction temperature range at –40°C to 130°C"Go
  • Changed "Storage temperature (Q1 devices) –40°C to 125°C" to "Storage temperatures, Tstg –65°C to 150°C"Go
  • Updated ESD Data Go
  • Changed the stereo line output load resistance MIN value in the Recommended Operating Conditions from "2 kΩ" to "1 kΩ"Go
  • Changed the operating junction temperature range in the Recommended Operating Conditionsfrom "MIN = –25°C MAX = 85°C" to "MIN = –40°C MAX = 130°C"Go
  • Added "Q1 Automotive grade devices..." and "Consumer grade (non-Q1) devices..." to the condition statement in the Electrical CharacteristicsGo
  • Changed "Gain error on Q1 Devices" to "Gain error on Q1 Automotive Grade Devices" in Electrical CharacteristicsGo
  • Changed min/max bipolar offset error for PCM5xx2 to be ±2 mV Go
  • Updated graph titles with device prefixGo
  • Added "Q1 Automotive grade devices..." and "Consumer grade (non-Q1) devices..." to the condition statement in the Typical Characteristics graphs section.Go
  • Changed "MCK" to "SCK" at the PLL Clock in the Functional Block DiagramGo
  • Added details to Zero Data Detection about the default behavior of the device Go
  • Added label "Mute Circuit" and ground symbols to pins DEMP and FMT in Figure 33Go
  • Added details about fast control of XSMT Go

Changes from A Revision (September 2012) to B Revision

  • Added ESD Rating table, Detailed Description section, Application and Implementation section, Power Supply Recommendations section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable InformationGo
  • Added items to show 1.8 V DVDD capabilityGo
  • Changed the Features list.Go
  • Changed "Operating temperature range " to "Operating junction temperature range"Go
  • Deleted redundant PLL specification in the Recommended Operating ConditionsGo
  • Deleted "Intelligent clock error..." and "...for pop-free performance."Go
  • Clarified clock generation explanationGo
  • Clarified external SCK discussion.Go
  • Deleted "The PCM510xA disables the internal PLL when an external SCK is supplied."Go

Changes from * Revision (May 2012) to A Revision

  • Changed layout of first two pagesGo
  • Changed "VOUT = –1 dB" to "THD+N at –1 dBFS" in in the Dymamic Performance section of the Electrical CharacteristicsGo
  • Changed reference to correct footnoteGo
  • Changed tSCKH and tSCKL values to 9ns.Go
  • Removed 48kHz sample rate with PLL-generated clockGo