JAJSKT0 December 2020 PCM6020-Q1
PRODUCTION DATA
Table 8-114 lists the memory-mapped registers for the Page 1 registers. All register offset addresses not listed in Table 8-114 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Reset Value | Section |
---|---|---|---|---|
0x0 | PAGE_CFG | Device page register | 0x00 | #PCM6020_PAGE_1_PAGE_1_PAGE_CFG |
0x16 | MBIAS_LOAD | MICBIAS internal load sink configuration register | 0x00 | #PCM6020_PAGE_1_PAGE_1_MBIAS_LOAD |
0x2C | INT_LIVE0 | Live interrupt readback register 0 | 0x00 | #PCM6020_PAGE_1_PAGE_1_INT_LIVE0 |
0x2D | CHx_LIVE | Channel diagnostic summary live status register | 0x00 | #PCM6020_PAGE_1_PAGE_1_CHX_LIVE |
0x2E | CH1_LIVE | Channel 1 diagnostic live status register | 0x00 | #PCM6020_PAGE_1_PAGE_1_CH1_LIVE |
0x2F | CH2_LIVE | Channel 2 diagnostic live status register | 0x00 | #PCM6020_PAGE_1_PAGE_1_CH2_LIVE |
0x35 | INT_LIVE1 | Live interrupt readback register 1 | 0x00 | #PCM6020_PAGE_1_PAGE_1_INT_LIVE1 |
0x37 | INT_LIVE3 | Live interrupt readback register 3 | 0x00 | #PCM6020_PAGE_1_PAGE_1_INT_LIVE3 |
0x55 | MBIAS_OV_CFG | MICBIAS overvoltage threshold register | 0x40 | #PCM6020_PAGE_1_PAGE_1_MBIAS_OV_CFG |
0x59 | DIAGDATA_CFG | Diagnostic data configuration register | 0x00 | #PCM6020_PAGE_1_PAGE_1_DIAGDATA_CFG |
0x5A | DIAG_MON_MSB_VBAT | Diagnostic VBAT_IN data MSB byte register | 0x00 | #PCM6020_PAGE_1_PAGE_1_DIAG_MON_MSB_VBAT |
0x5B | DIAG_MON_LSB_VBAT | Diagnostic VBAT_IN data LSB nibble register | 0x00 | #PCM6020_PAGE_1_PAGE_1_DIAG_MON_LSB_VBAT |
0x5C | DIAG_MON_MSB_MBIAS | Diagnostic MICBIAS data MSB byte register | 0x00 | #PCM6020_PAGE_1_PAGE_1_DIAG_MON_MSB_MBIAS |
0x5D | DIAG_MON_LSB_MBIAS | Diagnostic MICBIAS data LSB nibble register | 0x01 | #PCM6020_PAGE_1_PAGE_1_DIAG_MON_LSB_MBIAS |
0x5E | DIAG_MON_MSB_IN1P | Diagnostic IN1P data MSB byte register | 0x00 | #PCM6020_PAGE_1_PAGE_1_DIAG_MON_MSB_IN1P |
0x5F | DIAG_MON_LSB_IN1P | Diagnostic IN1P data LSB nibble register | 0x02 | #PCM6020_PAGE_1_PAGE_1_DIAG_MON_LSB_IN1P |
0x60 | DIAG_MON_MSB_IN1M | Diagnostic IN1M data MSB byte register | 0x00 | #PCM6020_PAGE_1_PAGE_1_DIAG_MON_MSB_IN1M |
0x61 | DIAG_MON_LSB_IN1M | Diagnostic IN1M data LSB nibble register | 0x03 | #PCM6020_PAGE_1_PAGE_1_DIAG_MON_LSB_IN1M |
0x62 | DIAG_MON_MSB_IN2P | Diagnostic IN2P data MSB byte register | 0x00 | #PCM6020_PAGE_1_PAGE_1_DIAG_MON_MSB_IN2P |
0x63 | DIAG_MON_LSB_IN2P | Diagnostic IN2P data LSB nibble register | 0x04 | #PCM6020_PAGE_1_PAGE_1_DIAG_MON_LSB_IN2P |
0x64 | DIAG_MON_MSB_IN2M | Diagnostic IN2M data MSB byte register | 0x00 | #PCM6020_PAGE_1_PAGE_1_DIAG_MON_MSB_IN2M |
0x65 | DIAG_MON_LSB_IN2M | Diagnostic IN2M data LSB nibble register | 0x05 | #PCM6020_PAGE_1_PAGE_1_DIAG_MON_LSB_IN2M |
0x76 | DIAG_MON_MSB_TEMP | Diagnostic temperature data MSB byte register | 0x00 | #PCM6020_PAGE_1_PAGE_1_DIAG_MON_MSB_TEMP |
0x77 | DIAG_MON_LSB_TEMP | Diagnostic temperature data LSB nibble register | 0x0E | #PCM6020_PAGE_1_PAGE_1_DIAG_MON_LSB_TEMP |
0x78 | DIAG_MON_MSB_LOAD | Diagnostic MICBIAS load current data MSB byte register | 0x00 | #PCM6020_PAGE_1_PAGE_1_DIAG_MON_MSB_LOAD |
0x79 | DIAG_MON_LSB_LOAD | Diagnostic MICBIAS load current data LSB nibble register | 0x0F | #PCM6020_PAGE_1_PAGE_1_DIAG_MON_LSB_LOAD |
0x7E | REV_ID | Silicon revision ID register | 0x20 | #PCM6020_PAGE_1_PAGE_1_REV_ID |
PAGE_CFG is shown in Figure 8-134 and described in Table 8-115.
Return to the Summary Table.
The device memory map is divided into pages. This register sets the page.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PAGE[7:0] | |||||||
R/W-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | PAGE[7:0] | R/W | 00000000b | These bits set the device page.
0d = Page 0 1d = Page 1 … 255d = Page 255 |
MBIAS_LOAD is shown in Figure 8-135 and described in Table 8-116.
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This register is the MICBIAS internal load sink configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MICBIAS_INT_LOAD_SINK_EN | MICBIAS_INT_LOAD_SINK_VAL[2:0] | RESERVED | |||||
R/W-0b | R/W-000b | R-0000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | MICBIAS_INT_LOAD_SINK_EN | R/W | 0b | MICBIAS internal load sink setting.
0d = MICBIAS internal load sink is enabled with setting automatically calculated based on device configuration 1d = MICBIAS internal load sink is enabled based on D6-4 register bits; This setting must be used for single-ended AC-coupled input to support high signal swing |
6-4 | MICBIAS_INT_LOAD_SINK_VAL[2:0] | R/W | 000b | MICBIAS internal load sink current value.
0d = MICBIAS internal load sink current is set to 0 mA (typ) 1d = MICBIAS internal load sink current is set to 4.3 mA (typ) 2d = MICBIAS internal load sink current is set to 8.6 mA (typ) 3d = MICBIAS internal load sink current is set to 12.9 mA (typ) 4d = MICBIAS internal load sink current is set to 17.2 mA (typ) 5d = MICBIAS internal load sink current is set to 21.5 mA (typ) 6d = MICBIAS internal load sink current is set to 25.8 mA (typ) 7d = MICBIAS internal load sink current is set to 30.1 mA (typ) |
3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset values |
INT_LIVE0 is shown in Figure 8-136 and described in Table 8-117.
Return to the Summary Table.
This register is the live Interrupt readback register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_LIVE0 | INT_LIVE0 | INT_LIVE0 | INT_LIVE0 | RESERVED | RESERVED | RESERVED | RESERVED |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_LIVE0 | R | 0b | Fault status for an ASI bus clock error.
0d = No fault detected 1d = Fault detected |
6 | INT_LIVE0 | R | 0b | Status of PLL lock.
0d = No PLL lock detected 1d = PLL lock detected |
5 | INT_LIVE0 | R | 0b | Fault status for boost or MICBIAS over temperature.
0d = No fault detected 1d = Fault detected |
4 | INT_LIVE0 | R | 0b | Fault status for boost or MICBIAS over current.
0d = No fault detected 1d = Fault detected |
3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
2 | RESERVED | R | 0b | Reserved bit; Write only reset value |
1 | RESERVED | R | 0b | Reserved bit; Write only reset value |
0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
CHx_LIVE is shown in Figure 8-137 and described in Table 8-118.
Return to the Summary Table.
This register is the live Interrupt status register for channel level diagnostic summary.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STS_CHx_LIVE | STS_CHx_LIVE | RESERVED | RESERVED | RESERVED | RESERVED | STS_CHx_LIVE | RESERVED |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | STS_CHx_LIVE | R | 0b | Status of CH1_LIVE.
0d = No faults occurred in channel 1 1d = Atleast a fault has occurred in channel 1 |
6 | STS_CHx_LIVE | R | 0b | Status of CH2_LIVE.
0d = No faults occurred in channel 2 1d = Atleast a fault has occurred in channel 2 |
5 | RESERVED | R | 0b | Reserved bit; Write only reset value |
4 | RESERVED | R | 0b | Reserved bit; Write only reset value |
3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
2 | RESERVED | R | 0b | Reserved bit; Write only reset value |
1 | STS_CHx_LIVE | R | 0b | Status of short to VBAT_IN fault detected when VBAT_IN is less than MICBIAS.
0d = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS has not occurred in any channel 1d = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS has occurred in atleast one channel |
0 | RESERVED | R | 0b | Reserved bit; Write only reset value |
CH1_LIVE is shown in Figure 8-138 and described in Table 8-119.
Return to the Summary Table.
This register is the live Interrupt status register for channel 1 fault diagnostic
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH1_LIVE | CH1_LIVE | CH1_LIVE | CH1_LIVE | CH1_LIVE | CH1_LIVE | CH1_LIVE | CH1_LIVE |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CH1_LIVE | R | 0b | Channel 1 open input fault status.
0d = No open input detected 1d = Open input detected |
6 | CH1_LIVE | R | 0b | Channel 1 input pair short fault status.
0d = No input pair short detected 1d = Input short to each other detected |
5 | CH1_LIVE | R | 0b | Channel 1 IN1P short to ground fault status.
0d = IN1P no short to ground detected 1d = IN1P short to ground detected |
4 | CH1_LIVE | R | 0b | Channel 1 IN1M short to ground fault status.
0d = IN1M no short to ground detected 1d = IN1M short to ground detected |
3 | CH1_LIVE | R | 0b | Channel 1 IN1P short to MICBIAS fault status.
0d = IN1P no short to MICBIAS detected 1d = IN1P short to MICBIAS detected |
2 | CH1_LIVE | R | 0b | Channel 1 IN1M short to MICBIAS fault status.
0d = IN1M no short to MICBIAS detected 1d = IN1M short to MICBIAS detected |
1 | CH1_LIVE | R | 0b | Channel 1 IN1P short to VBAT_IN fault status.
0d = IN1P no short to VBAT_IN detected 1d = IN1P short to VBAT_IN detected |
0 | CH1_LIVE | R | 0b | Channel 1 IN1M short to VBAT_IN fault status.
0d = IN1M no short to VBAT_IN detected 1d = IN1M short to VBAT_IN detected |
CH2_LIVE is shown in Figure 8-139 and described in Table 8-120.
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This register is the live Interrupt status register for channel 2 fault diagnostic.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH2_LIVE | CH2_LIVE | CH2_LIVE | CH2_LIVE | CH2_LIVE | CH2_LIVE | CH2_LIVE | CH2_LIVE |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CH2_LIVE | R | 0b | Channel 2 open input fault status.
0d = No open input detected 1d = Open input detected |
6 | CH2_LIVE | R | 0b | Channel 2 input pair short fault status.
0d = No input pair short detected 1d = Input short to each other detected |
5 | CH2_LIVE | R | 0b | Channel 2 IN2P short to ground fault status.
0d = IN2P no short to ground detected 1d = IN2P short to ground detected |
4 | CH2_LIVE | R | 0b | Channel 2 IN2M short to ground fault status.
0d = IN2M no short to ground detected 1d = IN2M short to ground detected |
3 | CH2_LIVE | R | 0b | Channel 2 IN2P short to MICBIAS fault status.
0d = IN2P no short to MICBIAS detected 1d = IN2P short to MICBIAS detected |
2 | CH2_LIVE | R | 0b | Channel 2 IN2M short to MICBIAS fault status.
0d = IN2M no short to MICBIAS detected 1d = IN2M short to MICBIAS detected |
1 | CH2_LIVE | R | 0b | Channel 2 IN2P short to VBAT_IN fault status.
0d = IN2P no short to VBAT_IN detected 1d = IN2P short to VBAT_IN detected |
0 | CH2_LIVE | R | 0b | Channel 2 IN2M short to VBAT_IN fault status.
0d = IN2M no short to VBAT_IN detected 1d = IN2M short to VBAT_IN detected |
INT_LIVE1 is shown in Figure 8-140 and described in Table 8-121.
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This register is the live Interrupt readback register 1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_LIVE1 | INT_LIVE1 | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-00b | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_LIVE1 | R | 0b | Channel 1 IN1P over voltage fault status.
0d = No IN1P over voltage fault detected 1d = IN1P over voltage fault has detected |
6 | INT_LIVE1 | R | 0b | Channel 2 IN2P over voltage fault status.
0d = No IN2P over voltage fault detected 1d = IN2P over voltage fault has detected |
5 | RESERVED | R | 0b | Reserved bit; Write only reset value |
4 | RESERVED | R | 0b | Reserved bit; Write only reset value |
3 | RESERVED | R | 0b | Reserved bit; Write only reset value |
2 | RESERVED | R | 0b | Reserved bit; Write only reset value |
1-0 | RESERVED | R | 00b | Reserved bits; Write only reset value |
INT_LIVE3 is shown in Figure 8-141 and described in Table 8-122.
Return to the Summary Table.
This register is the live Interrupt readback register 3.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_LIVE3 | INT_LIVE3 | INT_LIVE3 | RESERVED | ||||
R-0b | R-0b | R-0b | R-00000b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_LIVE3 | R | 0b | Fault status for MICBIAS high current.
0d = No fault detected 1d = Fault detected |
6 | INT_LIVE3 | R | 0b | Fault status for MICBIAS low current.
0d = No fault detected 1d = Fault detected |
5 | INT_LIVE3 | R | 0b | Fault status for MICBIAS over voltage.
0d = No fault detected 1d = Fault detected |
4-0 | RESERVED | R | 00000b | Reserved bits; Write only reset value |
MBIAS_OV_CFG is shown in Figure 8-142 and described in Table 8-123.
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This register is the MICBIAS overvoltage configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MBIAS_OV_THRES[2:0] | RESERVED | ||||||
R/W-010b | R-00000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | MBIAS_OV_THRES[2:0] | R/W | 010b | MICBIAS overvoltage fault detection threshold above MICBIAS programmed voltage.
0d = No threshold over programmed voltage 1d = 10mV (typ) threshold over programmed voltage 2d = 40mV (typ) threshold over programmed voltage (default) 3d to 6d = Threshold value is set as per configuration with step size of 30mV (typ) 7d = 190mV (typ) threshold over programmed voltage (default) |
4-0 | RESERVED | R | 00000b | Reserved bits; Write only reset value |
DIAGDATA_CFG is shown in Figure 8-143 and described in Table 8-124.
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This register is the diagnostic data configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | HOLD_SAR_DATA | |||||
R/W-0000b | R-000b | R/W-0b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | R/W | 0000b | Reserved bits; Write only reset values |
3-1 | RESERVED | R | 000b | Reserved bits; Write only reset values |
0 | HOLD_SAR_DATA | R/W | 0b | Hold SAR data update during register readback.
0d = Data update is not held, data register is continuously updated; this setting must be used when moving average is enabled for fault detection 1d = Data update is held, data register readback can be done |
DIAG_MON_MSB_VBAT is shown in Figure 8-144 and described in Table 8-125.
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This register is the MSB data byte of VBAT_IN monitoring.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_VBAT[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_VBAT[7:0] | R | 00000000b | Diagnostic SAR monitor data MSB byte. |
DIAG_MON_LSB_VBAT is shown in Figure 8-145 and described in Table 8-126.
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This register is the LSB data nibble of VBAT_IN monitoring.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_VBAT[3:0] | CHANNEL_ID[3:0] | ||||||
R-0000b | R-0000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_VBAT[3:0] | R | 0000b | Diagnostic SAR monitor data LSB nibble. |
3-0 | CHANNEL_ID[3:0] | R | 0000b | Channel ID value. |
DIAG_MON_MSB_MBIAS is shown in Figure 8-146 and described in Table 8-127.
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This register is the MSB data byte of MICBIAS monitoring.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_MBIAS[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_MBIAS[7:0] | R | 00000000b | Diagnostic SAR monitor data MSB byte. |
DIAG_MON_LSB_MBIAS is shown in Figure 8-147 and described in Table 8-128.
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This register is the LSB data nibble of MICBIAS monitoring.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_MBIAS[3:0] | CHANNEL_ID[3:0] | ||||||
R-0000b | R-0001b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_MBIAS[3:0] | R | 0000b | Diagnostic SAR monitor data LSB nibble. |
3-0 | CHANNEL_ID[3:0] | R | 0001b | Channel ID value. |
DIAG_MON_MSB_IN1P is shown in Figure 8-148 and described in Table 8-129.
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This register is the MSB data byte of IN1P monitoring.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_CH1P[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_CH1P[7:0] | R | 00000000b | Diagnostic SAR monitor data MSB byte. |
DIAG_MON_LSB_IN1P is shown in Figure 8-149 and described in Table 8-130.
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This register is the LSB data nibble of IN1P monitoring.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_CH1P[3:0] | CHANNEL_ID[3:0] | ||||||
R-0000b | R-0010b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_CH1P[3:0] | R | 0000b | Diagnostic SAR monitor data LSB nibble. |
3-0 | CHANNEL_ID[3:0] | R | 0010b | Channel ID value. |
DIAG_MON_MSB_IN1M is shown in Figure 8-150 and described in Table 8-131.
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This register is the MSB data byte of IN1M monitoring.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_CH1N[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_CH1N[7:0] | R | 00000000b | Diagnostic SAR monitor data MSB byte. |
DIAG_MON_LSB_IN1M is shown in Figure 8-151 and described in Table 8-132.
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This register is the LSB data nibble of IN1M monitoring.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_CH1N[3:0] | CHANNEL_ID[3:0] | ||||||
R-0000b | R-0011b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_CH1N[3:0] | R | 0000b | Diagnostic SAR monitor data LSB nibble. |
3-0 | CHANNEL_ID[3:0] | R | 0011b | Channel ID value. |
DIAG_MON_MSB_IN2P is shown in Figure 8-152 and described in Table 8-133.
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This register is the MSB data byte of IN2P monitoring.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_CH2P[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_CH2P[7:0] | R | 00000000b | Diagnostic SAR monitor data MSB byte. |
DIAG_MON_LSB_IN2P is shown in Figure 8-153 and described in Table 8-134.
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This register is the LSB data nibble of IN2P monitoring.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_CH2P[3:0] | CHANNEL_ID[3:0] | ||||||
R-0000b | R-0100b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_CH2P[3:0] | R | 0000b | Diagnostic SAR monitor data LSB nibble. |
3-0 | CHANNEL_ID[3:0] | R | 0100b | Channel ID value. |
DIAG_MON_MSB_IN2M is shown in Figure 8-154 and described in Table 8-135.
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This register is the MSB data byte of IN2M monitoring.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_CH2N[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_CH2N[7:0] | R | 00000000b | Diagnostic SAR monitor data MSB byte. |
DIAG_MON_LSB_IN2M is shown in Figure 8-155 and described in Table 8-136.
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This register is the LSB data nibble of IN2M monitoring.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_CH2N[3:0] | CHANNEL_ID[3:0] | ||||||
R-0000b | R-0101b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_CH2N[3:0] | R | 0000b | Diagnostic SAR monitor data LSB nibble. |
3-0 | CHANNEL_ID[3:0] | R | 0101b | Channel ID value. |
DIAG_MON_MSB_TEMP is shown in Figure 8-156 and described in Table 8-137.
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This register is the MSB data byte of temperature monitoring.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_TEMP[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_TEMP[7:0] | R | 00000000b | Diagnostic SAR monitor data MSB byte. |
DIAG_MON_LSB_TEMP is shown in Figure 8-157 and described in Table 8-138.
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This register is the LSB data nibble of temperature monitoring.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_TEMP[3:0] | CHANNEL_ID[3:0] | ||||||
R-0000b | R-1110b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_TEMP[3:0] | R | 0000b | Diagnostic SAR monitor data LSB nibble. |
3-0 | CHANNEL_ID[3:0] | R | 1110b | Channel ID value. |
DIAG_MON_MSB_LOAD is shown in Figure 8-158 and described in Table 8-139.
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This register is the MSB data byte of MICBIAS load current monitoring.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_MSB_LOAD[7:0] | |||||||
R-00000000b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIAG_MON_MSB_LOAD[7:0] | R | 00000000b | Diagnostic SAR monitor data MSB byte. |
DIAG_MON_LSB_LOAD is shown in Figure 8-159 and described in Table 8-140.
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This register is the LSB data nibble of MICBIAS load current monitoring.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIAG_MON_LSB_LOAD[3:0] | CHANNEL_ID[3:0] | ||||||
R-0000b | R-1111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DIAG_MON_LSB_LOAD[3:0] | R | 0000b | Diagnostic SAR monitor data LSB nibble. |
3-0 | CHANNEL_ID[3:0] | R | 1111b | Channel ID value. |
REV_ID is shown in Figure 8-160 and described in Table 8-141.
Return to the Summary Table.
This register is the silicon revision ID register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV_ID[3:0] | RESERVED | ||||||
R-0010b | R-0000b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | REV_ID[3:0] | R | 0010b | Returns the revision ID. |
3-0 | RESERVED | R | 0000b | Reserved bits; Write only reset values |