SBAS884A March 2020 – June 2020 PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1 , PCM6360-Q1
PRODUCTION DATA.
This register is the ASI configuration register 0.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ASI_FORMAT[1:0] | ASI_WLEN[1:0] | FSYNC_POL | BCLK_POL | TX_EDGE | TX_FILL | ||
RW-0h | RW-3h | RW-0h | RW-0h | RW-0h | RW-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | ASI_FORMAT[1:0] | RW | 0h | ASI protocol format.
0d = TDM mode 1d = I2S mode 2d = LJ (left-justified) mode 3d = Reserved |
5-4 | ASI_WLEN[1:0] | RW | 3h | ASI word or slot length.
0d = 16 bits 1d = 20 bits 2d = 24 bits 3d = 32 bits |
3 | FSYNC_POL | RW | 0h | ASI FSYNC polarity.
0d = Default polarity as per standard protocol 1d = Inverted polarity with respect to standard protocol |
2 | BCLK_POL | RW | 0h | ASI BCLK polarity.
0d = Default polarity as per standard protocol 1d = Inverted polarity with respect to standard protocol |
1 | TX_EDGE | RW | 0h | ASI data output (on the primary and secondary data pin) transmit edge.
0d = Default edge as per the protocol configuration setting in bit 2 (BCLK_POL) 1d = Inverted following edge (half cycle delay) with respect to the default edge setting |
0 | TX_FILL | RW | 0h | ASI data output (on the primary and secondary data pin) for any unused cycles
0d = Always transmit 0 for unused cycles 1d = Always use Hi-Z for unused cycles |