PGA2310 Stereo Audio Volume Control

1 Features

Digitally-Controlled Analog Volume Control:
- Two Independent Audio Channels
- Serial Control Interface
- Zero Crossing Detection
- Mute Function
Wide Gain and Attenuation Range: 31.5 dB to −95.5 dB With 0.5-dB Steps
Low Noise and Distortion:
- 120-dB Dynamic Range
- 0.0004% THD+N at 1 kHz
Low Interchannel Crosstalk: −126 dBFS
Noise-Free Level Transitions
Power Supplies: 15-V Analog, 5-V Digital
Available in DIP−16 and SOL−16 Packages
Pin and Software Compatible With the PGA2311 and Cirrus Logic CS3310™

2 Applications

Audio Amplifiers
Mixing Consoles
Multi-Track Recorders
Broadcast Studio Equipment
Musical Instruments
Effects Processors
A/V Receivers
Car Audio Systems

3 Description

The PGA2310 is a high-performance, stereo audio volume control designed for professional and high-end consumer audio systems. The ability to operate from ±15-V analog power supplies enables the PGA2310 to process input signals with large voltage swings, thereby preserving the dynamic range available in the overall signal path. Using high performance operational amplifier stages internal to the PGA2310 yields low noise and distortion, while providing the capability to drive 600-Ω loads directly without buffering. The three-wire serial control interface allows for connection to a wide variety of host controllers, in addition to support for daisy-chaining multiple PGA2310 devices.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
PGA2310	SOIC (16)	7.50 mm × 10.30 mm
PGA2310	PDIP (16)	6.35 mm × 19.30 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Stereo Audio Volume Control

4 Revision History

Changes from B Revision (June 2004) to C Revision

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go

5 Pin Configuration and Functions

D and P Pakcages

16 Pins SOIC and PDIP

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NO.	NAME	I/O	DESCRIPTION
1	ZCEN	I	Zero Crossing Enable Input (Active High)
2	CS	I	Chip Select Input (Active Low)
3	SDI	I	Serial Data Input
4	V_D+	I	Digital Power Supply, 5 V
5	DGND	—	Digital Ground
6	SCLK	I	Serial Clock Input
7	SDO	O	Serial Data Output
8	MUTE	I	Mute Control Input (Active Low)
9	V_INR	I	Analog Input, Right Channel
10	AGNDR	—	Analog Ground, Right Channel
11	V_OUTR	O	Analog Output, Right Channel
12	V_A+	I	Analog Power Supply, 15 V
13	V_A–	I	Analog Power Supply, –15 V
14	V_OUTL	O	Analog Output, Left Channel
15	AGNDL	—	Analog Ground, Left Channel
16	V_INL	I	Analog Input, Left Channel