8.3.1.2 Input Amplifier, Gain Network, and Buffer

The high-precision input amplifiers present very low dc error and drift as a result of a modern chopper technology with an embedded synchronous filter that removes virtually all chopping noise. This topology reduces flicker noise to a minimum and therefore enables the precise measurement of small dc-signals with high resolution, accuracy, and repeatability. The chopper frequency of 250 kHz is derived from an internal 1-MHz clock. An external clock can also be connected, if desired.

The gain network for the binary gain steps connects to the input amplifiers, thus providing the best possible signal-to-noise ratio (SNR) and dc accuracy up to the highest gains. Gain is controlled by Register 0. This register can control the gain and address for an external MUX in one byte. Selectable gains (in V/V) are : 128, 64, 32, 16, 8, 4, 2, 1, ½, ¼, and ⅛. The gain is set to 1/8 V/V after device reset or power-on.

Programmable gain amplifiers such as the PGA280 use internal resistors to set the gain. Consequently, quiescent current is increased by the current that passes through these resistors. The largest amplitude could increase the supply current by ±0.4 mA. In maximum overload, gain of 128 V/V and each or the inputs connected to the opposite supply voltage, a current of approximately 27 mA was measured. External resistors in series with the input pins that are normally present avoid this extreme condition. This current is only limited by the internal 600 Ω and the switch-on resistance (see Figure 44).