JAJSIV0B June   2009  – March 2020 PGA280

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Electrical Characteristics
    3. 7.3 Timing Requirements: Serial Interface
    4. 7.4 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Functional Blocks
        1. 8.3.1.1 Input Switch Network
        2. 8.3.1.2 Input Amplifier, Gain Network, and Buffer
        3. 8.3.1.3 Current Buffer
        4. 8.3.1.4 Input Protection
        5. 8.3.1.5 EMI Susceptibility
        6. 8.3.1.6 Output Stage
        7. 8.3.1.7 Output Filter
        8. 8.3.1.8 Single-Ended Output
        9. 8.3.1.9 Error Detection
      2. 8.3.2 Error Indicators
        1. 8.3.2.1 Input Clamp Conduction (ICAerr)
        2. 8.3.2.2 Input Overvoltage (IOVerr)
        3. 8.3.2.3 Gain Network Overload (GAINerr)
        4. 8.3.2.4 Output Amplifier (OUTerr)
        5. 8.3.2.5 CheckSum Error (CRCerr)
    4. 8.4 Device Functional Modes
      1. 8.4.1 GPIO Operation Mode
        1. 8.4.1.1 CS Mode
    5. 8.5 Programming
      1. 8.5.1 SPI and Register Description
      2. 8.5.2 Command Structure and Register Overview
        1. 8.5.2.1 Command Byte
        2. 8.5.2.2 Extended CS
          1. 8.5.2.2.1 SPI Timing Diagrams (Read and Write)
          2. 8.5.2.2.2 GPIO Pin Reference
          3. 8.5.2.2.3 Checksum
      3. 8.5.3 GPIO Configuration
      4. 8.5.4 Buffer Timing
    6. 8.6 Register Map
      1. 8.6.1  Register 0: Gain and External MUX Address (address = 00h) [reset = 0000 0000b]
      2. 8.6.2  Register 1: Software Reset Register (address = 01h) [reset = 0000 0000b]
      3. 8.6.3  Register 2: SPI: MODE Selection to GPIO-Pin (address = 02h) [reset = 0000 0000b]
      4. 8.6.4  Register 3: BUF Timeout Register (address = 03h) [reset = 0001 1001b]
      5. 8.6.5  Register 4: Error Register (address = 04h) [reset = 0000 0000b]
      6. 8.6.6  Register 5: GPIO Register (address = 05h) [reset = 0000 0000b]
      7. 8.6.7  Register 6: Input Switch Control Register 1 (address = 06h) [reset = 0110 0000b]
      8. 8.6.8  Register 7: Input Switch Control Register 2 (address =07h ) [reset = 0000 0000b]
      9. 8.6.9  Register 8: GPIO Configuration Register (address = 08h) [reset = 0000 0000b]
      10. 8.6.10 Register 9: CS Configuration Mode Register (address = 09h) [reset = 0000 0000b]
      11. 8.6.11 Register 10: Configuration Register 1 (address = 0Ah) [reset = 0000 0000b]
      12. 8.6.12 Register 11: Configuration Register 2 (address = 0Bh) [reset = 0001 0000b]
      13. 8.6.13 Register 12: Special Functions Register (address = 0Ch) [reset = 0000 0000b]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 External Clock Synchronization
      2. 9.1.2 Quiescent Current
      3. 9.1.3 Settling Time
      4. 9.1.4 Overload Recovery
  10. 10Power Supply Recommendations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5.4 Buffer Timing

The buffer is used to isolate fast transients from the overload protection of the high-precision amplifier. The buffer avoids current into the overload clamp. Fast transients result from the switching transient of a signal multiplexer or a gain change; these transients cannot be filtered in the signal path.

The buffer can be turned on by software using the T bit in the SPI command or by activating a GPIO pin. The on-time of the buffer is set in Register 3 (BUFTIM).

If controlled by software command, the buffer turns active (indicated by BUFA shown in Figure 55) with the last falling edge of SCLK.

Controlling an external MUX through Register 0 activates the GPIO pins after the rising edge of CS, providing an extra delay.

Alternatively, the buffer can be controlled by GPIO4, after configuration (Register 8, bit 4 = 0, and 0x4C10). A rising edge triggers the buffer with a delay of three to four clock cycles. If held high, the buffer [BUFA] remains active. The active time is extended by a minimum of three to four clock cycles plus FLAGTIM.

The buffer active condition can be observed at GPIO5, after configuration for output and special function (0x4820, 0x4C20). The time reference is the end of CS. The buffer is turned on with the 16th falling edge of the SCLK and writing to Register 0 (0x6018). BUFA stays high for 6 μs (BUFTIM0) after CS.

PGA280 ai_dig_gpio_bos487.gifFigure 55. BUFA Timing