SBVS046D December   2003  – March 2016 REF3112 , REF3120 , REF3125 , REF3130 , REF3133 , REF3140

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Supply Voltage
      2. 8.3.2 Thermal Hysteresis
      3. 8.3.3 Temperature Drift
      4. 8.3.4 Noise Performance
      5. 8.3.5 Long-Term Stability
      6. 8.3.6 Load Regulation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Negative Reference Voltage
      2. 8.4.2 Data Acquisition
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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発注情報

11 Layout

11.1 Layout Guidelines

Figure 33 illustrates an example of a printed-circuit board (PCB) layout using the REF31xx. Some key considerations are:

  • Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN of the REF31xx
  • Decouple other active devices in the system per the device specifications
  • Use a solid ground plane to help distribute heat and reduces electromagnetic interference (EMI) noise pickup
  • Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring
  • Minimize trace length between the reference and bias connections to the INA and ADC to reduce noise pickup
  • Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary

11.2 Layout Example

REF3112 REF3120 REF3125 REF3130 REF3133 REF3140 sbvs046_Layout_REF31xx.gif Figure 33. Layout Example