SLAS834C November   2012  – December 2014 RF430FRL152H , RF430FRL153H , RF430FRL154H

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
    3. 4.3 Pin Multiplexing
    4. 4.4 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Recommended Operating Conditions, Resonant Circuit
    5. 5.5  Active Mode Supply Current Into VDDB Excluding External Current
    6. 5.6  Low-Power Mode Supply Current (Into VDDB) Excluding External Current
    7. 5.7  Digital I/Os (P1, RST/NMI)
    8. 5.8  High-Frequency Oscillator (4 MHz), HFOSC
    9. 5.9  Low-Frequency Oscillator (256 kHz), LFOSC
    10. 5.10 Wake-Up From Low-Power Modes
    11. 5.11 Timer_A
    12. 5.12 eUSCI (SPI Master Mode) Recommended Operating Conditions
    13. 5.13 eUSCI (SPI Master Mode)
    14. 5.14 eUSCI (SPI Slave Mode)
    15. 5.15 eUSCI (I2C Mode)
    16. 5.16 FRAM
    17. 5.17 JTAG
    18. 5.18 RFPMM, Power Supply Switch
    19. 5.19 RFPMM, Bandgap Reference
    20. 5.20 RFPMM, Voltage Doubler
    21. 5.21 RFPMM, Voltage Supervision
    22. 5.22 SD14, Performance
    23. 5.23 SVSS Generator
    24. 5.24 Thermistor Bias Generator
    25. 5.25 Temperature Sensor
    26. 5.26 RF13M, Power Supply and Recommended Operating Conditions
    27. 5.27 RF13M, ISO/IEC 15693 ASK Demodulator
    28. 5.28 RF13M, ISO/IEC 15693 Compliant Load Modulator
  6. 6Detailed Description
    1. 6.1 CPU
    2. 6.2 Instruction Set
    3. 6.3 Operating Modes
    4. 6.4 Interrupt Vector Addresses
    5. 6.5 Memory
      1. 6.5.1 FRAM
      2. 6.5.2 SRAM
      3. 6.5.3 Application ROM
    6. 6.6 Peripherals
      1. 6.6.1  Digital I/O, (P1.x)
      2. 6.6.2  Versatile I/O Port P1
      3. 6.6.3  Oscillator and System Clock
      4. 6.6.4  Compact System Module (C-SYS_A)
      5. 6.6.5  Watchdog Timer (WDT_A)
      6. 6.6.6  Reset, NMI, SVMOUT System
      7. 6.6.7  Timer_A (Timer0_A3)
      8. 6.6.8  Enhanced Universal Serial Communication Interface (eUSCI_B0)
      9. 6.6.9  ISO/IEC 15693 Analog Front End (RF13M)
      10. 6.6.10 ISO/IEC 15693 Decoder/Encoder (RF13M)
      11. 6.6.11 CRC16 Module (CRC16)
      12. 6.6.12 14-Bit Sigma-Delta ADC (SD14)
      13. 6.6.13 Programmable Gain Amplifier (SD14)
      14. 6.6.14 Peripheral Register Map
    7. 6.7 Port Schematics
      1. 6.7.1 Port P1.0 Input/Output
      2. 6.7.2 Port P1.1 Input/Output
      3. 6.7.3 Port P1.2 Input/Output
      4. 6.7.4 Port P1.3 Input/Output
      5. 6.7.5 Port P1.4 Input/Output
      6. 6.7.6 Port P1.5 Input/Output
      7. 6.7.7 Port P1.6 Input/Output
      8. 6.7.8 Port P1.7 Input/Output
    8. 6.8 Device Descriptors (TLV)
  7. 7Applications, Implementation, and Layout
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device and Development Tool Nomenclature
    2. 8.2 Documentation Support
    3. 8.3 Related Links
    4. 8.4 Community Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Mechanical Packaging and Orderable Information

9.1 Packaging Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.