JAJSL60F April 1977 – January 2021 SG2524 , SG3524
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
COL 1 | 12 | O | Collector terminal of BJT output 1 |
COL 2 | 13 | O | Collector terminal of BJT output 2 |
COMP | 9 | I/O | Error amplifier compensation pin |
CT | 7 | — | Capacitor terminal used to set oscillator frequency |
CURR LIM+ | 4 | I | Positive current limiting amplifier input |
CURR LIM- | 5 | I | Negative current limiting amplifier input |
EMIT 1 | 11 | O | Emitter terminal of BJT output 1 |
EMIT 2 | 14 | O | Emitter terminal of BJT output 2 |
GND | 8 | — | Ground |
IN+ | 2 | I | Positive error amplifier input |
IN- | 1 | I | Positive error amplifier input |
OSC OUT | 3 | O | Oscillator Output |
REF OUT | 16 | O | Reference regulator output |
RT | 6 | — | Resistor terminal used to set oscillator frequency |
SHUTDOWN | 10 | I | Device shutdown |
VCC | 15 | — | Positive supply |