SDLS025D December   1983  – May 2017 SN5400 , SN54LS00 , SN54S00 , SN7400 , SN74LS00 , SN74S00

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings: SN74LS00
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: SNx400
    6. 6.6  Electrical Characteristics: SNx4LS00
    7. 6.7  Electrical Characteristics: SNx4S00
    8. 6.8  Switching Characteristics: SNx400
    9. 6.9  Switching Characteristics: SNx4LS00
    10. 6.10 Switching Characteristics: SNx4S00
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delays, Setup and Hold Times, and Pulse Width
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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発注情報

11 Layout

11.1 Layout Guidelines

When using multiple bit logic, devices inputs must never float.

Devices with multiple-emitter inputs (SN74 and SN74S series) need special care. Because no voltage greater than 5.5 V must be applied to the inputs (if exceeded, the base-emitter junction at the inputs breaks down), the inputs of these devices must be connected to the supply voltage, VCC, through series resistor, RS (see Figure 5). This resistor must be dimensioned such that the current flowing into the gate or gates, which results from overvoltage, does not exceed 1 mA. However, because the high-level input current of the circuits connected to the gate flows through this resistor, the resistor must be dimensioned so that the voltage drop across it still allows the required high level. Equation 1 and Equation 2 are for dimensioning resistor, RS, and several inputs can be connected to a high level through a single resistor if the following conditions are met.

Equation 1. SN5400 SN54LS00 SN54S00 SN7400 SN74LS00 SN74S00 SDLS025D_equation_1.gif
Equation 2. SN5400 SN54LS00 SN54S00 SN7400 SN74LS00 SN74S00 SDLS025D_equation_2.gif

where

  • n = number of inputs connected
  • IIH = high input current (typical 40 µA)
  • VCC(min) = minimum supply voltage, VCC
  • VCCP = maximum peak voltage of the supply voltage, VCC (about 7 V)

11.2 Layout Example

SN5400 SN54LS00 SN54S00 SN7400 SN74LS00 SN74S00 SDLS025D_Layout.gif Figure 5. Series Resistor Connected to Unused Inputs of Multiple-Emitter Transistors