JAJSTF3U January   1993  – July 2024 SN54LVC00A , SN74LVC00A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions, SN54LVC00A
    4. 5.4  Recommended Operating Conditions, SN74LVC00A
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics, SN54LVC00A
    7. 5.7  Electrical Characteristics, SN74LVC00A
    8. 5.8  Switching Characteristics, SN54LVC00A
    9. 5.9  Switching Characteristics, SN74LVC00A
    10. 5.10 Operating Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced High-Drive CMOS Push-Pull Outputs
      2. 7.3.2 Standard CMOS Inputs
      3. 7.3.3 Clamp Diodes
      4. 7.3.4 Over-voltage Tolerant Inputs
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3.     Power Supply Recommendations
    4. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Links
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
      1. 9.3.1 Community Resources
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 1046
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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発注情報

7.3.3 Clamp Diodes

The inputs and outputs to this device have negative clamping diodes.

CAUTION:

Voltages beyond the values specified in the Section 5.1 table can cause damage to the device. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

SN54LVC00A SN74LVC00A Electrical Placement of Clamping Diodes for Each Input and OutputFigure 7-2 Electrical Placement of Clamping Diodes for Each Input and Output