JAJSG48Q July   1995  – September 2018 SN54LVCH245A , SN74LVCH245A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Assignments: ZQN Package
    3.     Pin Assignments: ZXY Package
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions: SN74LVCH245A
    4. 6.4  Recommended Operating Conditions: SN54LVCH245A
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics: SN74LVCH245A
    7. 6.7  Electrical Characteristics: SN54LVCH245A
    8. 6.8  Switching Characteristics: SN74LVCH245A, –40°C TO 85°C
    9. 6.9  Switching Characteristics: SN74LVCH245A, –40°C TO 125°C
    10. 6.10 Switching Characteristics: SN54LVCH245A
    11. 6.11 Operating Characteristics
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
      2. 8.3.2 Standard CMOS Inputs
      3. 8.3.3 Negative Clamping Diodes
      4. 8.3.4 Bus-Hold Data Inputs
      5. 8.3.5 Partial Power Down (Ioff)
      6. 8.3.6 Over-voltage Tolerant Inputs
      7. 8.3.7 Output Enable
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連リンク
    2. 12.2 商標
    3. 12.3 静電気放電に関する注意事項
    4. 12.4 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • W|20
  • J|20
  • FK|20
サーマルパッド・メカニカル・データ
発注情報

6.6 Electrical Characteristics: SN74LVCH245A

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC –40°C TO 85°C –40°C TO 125°C UNIT
MIN TYP(1) MAX MIN TYP(1) MAX
VOH High-level
output voltage		 IOH = –100 µA 1.65 V to 3.6 V VCC  – 0.2 VCC  – 0.2 V
IOH = –4 mA 1.65 V 1.2 1.2
IOH = –8 mA 2.3 V 1.7 1.7
IOH = –12 mA 2.7 V 2.2 2.2
3 V 2.4 2.4
IOH = –24 mA 3 V 2.2 2.2
VOL Low-level
output voltage		 IOL = 100 µA 1.65 V to 3.6 V 0.2 0.20 V
IOL = 4 mA 1.65 V 0.45 0.45
IOL = 8 mA 2.3 V 0.7 0.7
IOL = 12 mA 2.7 V 0.4 0.4
IOL = 24 mA 3 V 0.55 0.55
II Input current Control inputs:
VI = 0 to 5.5 V		 3.6 V ±5 ±5 µA
Ioff Input and output
power-off
leakage current		 VI or VO = 5.5 V 0 V ±10 ±20 µA
II(hold) Input hold current VI = 0.58 V 1.65 V 25 25 µA
VI = 1.07 V –25 –25
VI = 0.7 V 2.3 V 45 45
VI = 1.7 V –45 –45
VI = 0.8 V 3 V 75 75
VI = 2 V –75 –75
VI = 0 to 3.6 V(2) 3.6 V ±500 ±500
IOZ(3) High-impedance state output current VO = 0 V or (VCC to 5.5 V) 2.3 V to 3.6 V ±5 ±15 µA
ICC Supply current VI = VCC or GND IO = 0 3.6 V 10 10 µA
3.6 V ≤ VI ≤ 5.5 V(4) IO = 0 3.6 V 10 10
ΔICC Supply-current change One input at VCC  – 0.6 V, other inputs at VCC or GND 2.7 V to 3.6 V 500 500 µA
Ci Input capacitance Control inputs:
VI = VCC or GND		 3.3 V 4 pF
Cio Input and output
capacitance		 A or B port:
VO = VCC or GND		 3.3 V 5.50 pF
(1) All typical values are VCC = 3.3 V, TA = 25°C.
(2) The bus-hold maximum dynamic current requirement to switch the input from one state to another state.
(3) For the total leakage current in an I/O port, see the II(hold) specification for the input voltage condition 0 V < VI < VCC, and the IOZ specification for the input voltage conditions VI = 0 V or VI = VCC to 5.5 V. A bus-hold current with an input voltage greater than VCC is negligible.
(4) This only applies when in a disabled state.