JAJSNL8B February   2022  – December 2023 SN54SLC8T245-SEP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics, VCCA = 0.7 V
    7. 5.7  Switching Characteristics, VCCA = 0.8 V
    8. 5.8  Switching Characteristics, VCCA = 0.9 V
    9. 5.9  Switching Characteristics, VCCA = 1.2 V
    10. 5.10 Switching Characteristics, VCCA = 1.5 V
    11. 5.11 Switching Characteristics, VCCA = 1.8 V
    12. 5.12 Switching Characteristics, VCCA = 2.5 V
    13. 5.13 Switching Characteristics, VCCA = 3.3 V
    14. 5.14 Operating Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Up-Translation and Down-Translation From 0.65 V to 3.6 V
      2. 7.3.2 Multiple Direction Control Pins
      3. 7.3.3 Ioff Supports Partial-Power-Down Mode Operation
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|24
サーマルパッド・メカニカル・データ
発注情報

6 Parameter Measurement Information

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

  • f =1 MHz
  • Z0 = 50 Ω
  • dv / dt ≤ 1 ns/V

GUID-2D5AFCD0-BE3C-438B-9DB0-88EFF4CD907B-low.gif
A. CL includes probe and jig capacitance.
Figure 6-1 Load Circuit
GUID-6E0E7E00-3CAA-4ADC-9837-9D87E9EF423B-low.gif
A. Output waveform on the conditions that input is driven to a valid Logic Low.
B. Output waveform on the condition that input is driven to a valid Logic High.
Figure 6-2 Load Circuit Conditions
GUID-F1C9D0DB-EEFA-4DA8-A176-D06E69C1ED0D-low.gif
A. VCCI is the supply pin associated with the input port.
B. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 6-3 Propagation Delay
GUID-FB9C9397-9694-4725-80CD-A85F48EAB93F-low.gif
A. Output waveform on the condition that input is driven to a valid Logic Low.
B. Output waveform on the condition that input is driven to a valid Logic High.
C. VCCO is the supply pin associated with the output port.
D. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 6-4 Enable Time And Disable Time