JAJSL15N July   1997  – April 2021 SN55LVDS31 , SN65LVDS31 , SN65LVDS3487 , SN65LVDS9638

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings #GUID-35E89C88-1E48-404C-8AB6-22CCA817C2ED/SLLS2613609
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: SN55LVDS31
    6. 7.6 Electrical Characteristics: SN65LVDSxxxx
    7. 7.7 Switching Characteristics: SN55LVDS31
    8. 7.8 Switching Characteristics: SN65LVDSxxxx
    9. 7.9 Typical Characteristics
      1. 7.9.1 17
  8. 8 Parameter Measurement Information
    1. 8.1 19
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Driver Disabled Output
      2. 9.3.2 NC Pins
      3. 9.3.3 Unused Enable Pins
      4. 9.3.4 Driver Equivalent Schematics
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Point-to-Point Communications
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Driver Supply Voltage
          2. 10.2.1.2.2 Driver Bypass Capacitance
          3. 10.2.1.2.3 Driver Output Voltage
          4. 10.2.1.2.4 Interconnecting Media
          5. 10.2.1.2.5 PCB Transmission Lines
          6. 10.2.1.2.6 Termination Resistor
          7. 10.2.1.2.7 Driver NC Pins
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Multidrop Communications
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Interconnecting Media
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 49
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Microstrip vs. Stripline Topologies
      2. 12.1.2 Dielectric Type and Board Construction
      3. 12.1.3 Recommended Stack Layout
      4. 12.1.4 Separation Between Traces
      5. 12.1.5 Crosstalk and Ground Bounce Minimization
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Other LVDS Products
    2. 13.2 Documentation Support
      1. 13.2.1 Related Information
      2. 13.2.2 ドキュメントの更新通知を受け取る方法
      3. 13.2.3 Related Links
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • W|16
  • J|16
  • FK|20
サーマルパッド・メカニカル・データ
発注情報

7.4 Thermal Information

THERMAL METRIC(1)SN55LVDS31SN65LVDS31SN65LVDS3487SN65LVDS9638UNIT
FKJWDNSPWDPWDDGKDGN(2)
20 PINS16 PINS16 PINS16 PINS16 PINS16 PINS16 PINS16 PINS8 PINS8 PINS8 PINS
RθJAJunction-to-ambient thermal resistance84.886.0179.5°C/W
RθJC(top)Junction-to-case (top) thermal resistance46.044.272.3
RθJBJunction-to-board thermal resistance41.826.4101.5
ψJTJunction-to-top characterization parameter11.110.911
ψJBJunction-to-board characterization parameter41.546.199.7
Power RatingTA ≤ 25°C137513751000950—7749507747254252140mW
TA ≤ 70°C880880640608—4966084964642721370
TA ≤ 85°C715715520494—4024944023772211110
TA ≤ 125°C275275200——-——————
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The PowerPAD™ must be soldered to a thermal land on the printed-circuit board. See the application note PowerPAD Thermally Enhanced Package (SLMA002).