JAJSHI0I February   2012  – January 2021 SN6501

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 説明
    1.     Revision History
  4. Pin Configuration and Functions
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  6. Parameter Measurement Information
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Push-Pull Converter
      2. 7.3.2 Core Magnetization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-Up Mode
      2. 7.4.2 Operating Mode
      3. 7.4.3 Off-Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 SN6501 Drive Capability
        2. 8.2.2.2 LDO Selection
        3. 8.2.2.3 Diode Selection
        4. 8.2.2.4 Capacitor Selection
        5. 8.2.2.5 Transformer Selection
          1. 8.2.2.5.1 V-t Product Calculation
          2. 8.2.2.5.2 Turns Ratio Estimate
          3. 8.2.2.5.3 Recommended Transformers
      3. 8.2.3 Application Curve
      4. 8.2.4 Higher Output Voltage Designs
      5. 8.2.5 Application Circuits
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 Trademarks
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout Guidelines

  • The VIN pin must be buffered to ground with a low-ESR ceramic bypass-capacitor. The recommended capacitor value can range from 1 μF to 10 μF. The capacitor must have a voltage rating of 10 V minimum and a X5R or X7R dielectric.
  • The optimum placement is closest to the VIN and GND pins at the board entrance to minimize the loop area formed by the bypass-capacitor connection, the VIN terminal, and the GND pin. See Figure 10-1 for a PCB layout example.
  • The connections between the device D1 and D2 pins and the transformer primary endings, and the connection of the device VCC pin and the transformer center-tap must be as close as possible for minimum trace inductance.
  • • The connection of the device VCC pin and the transformer center-tap must be buffered to ground with a low-ESR ceramic bypass-capacitor. The recommended capacitor value can range from 1μF to 10 μF. The capacitor must have a voltage rating of 16 V minimum and a X5R or X7R dielectric.
  • The device GND pins must be tied to the PCB ground plane using two vias for minimum inductance.
  • The ground connections of the capacitors and the ground plane should use two vias for minimum inductance.
  • The rectifier diodes should be Schottky diodes with low forward voltage in the 10 mA to 100 mA current range to maximize efficiency.
  • The VOUT pin must be buffered to ISO-Ground with a low-ESR ceramic bypass-capacitor. The recommended capacitor value can range from 1μF to 10 μF. The capacitor must have a voltage rating of 16 V minimum and a X5R or X7R dielectric.