JAJSGI2I september   2015  – august 2023 SN6505A , SN6505B

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics, SN6505A
    8. 6.8 Typical Characteristics, SN6505B
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Push-Pull Converter
      2. 8.3.2 Core Magnetization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Start-Up Mode
        1. 8.4.1.1 Soft-Start
      2. 8.4.2 Operating Mode
      3. 8.4.3 Shutdown-Mode
      4. 8.4.4 Spread Spectrum Clocking
      5. 8.4.5 External Clock Mode
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Drive Capability
        2. 9.2.2.2 LDO Selection
        3. 9.2.2.3 Diode Selection
        4. 9.2.2.4 Capacitor Selection
        5. 9.2.2.5 Transformer Selection
          1. 9.2.2.5.1 V-t Product Calculation
          2. 9.2.2.5.2 Turns Ratio Estimate
          3. 9.2.2.5.3 Recommended Transformers
      3. 9.2.3 Application Curves
      4. 9.2.4 System Examples
        1. 9.2.4.1 Higher Output Voltage Designs
        2. 9.2.4.2 Application Circuits
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

over full-range of recommended operating conditions, unless otherwise noted. All typical values are at TA = 25°C, VCC = 5 V.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VOLTAGE SUPPLY
I(Vcc)Supply Current (2.8 V < VCC < 5.5) (SN6505A)RL = 50 Ω11.4mA
Supply Current (2.8 V < VCC < 5.5) (SN6505B)RL = 50 Ω1.562.3mA
IIHLeakage Current on EN and CLK pinEN / CLK = VCC1020µA
IDISVCC current for EN = 00.1µA
ILKG(D1)
ILKG(D2)		Leakage Current on D1,D2 for EN=0Voltage of D1,D2 = VCC0.1µA
VCC+ (UVLO)Positive-going UVLO threshold2.25V
VCC- (UVLO)Negative-going UVLO threshold1.7V
VHYS (UVLO1)UVLO threshold hysteresis0.3V
VIN(ON)EN, CLK pin logic high threshold0.7VCC
VIN(OFF)EN, CLK pin logic low threshold0.3VCC
VIN(HYS)EN, CLK pin threshold hysteresis0.2VCC
CLK
FSWD1, D2 average switching Frequency (SN6505A)RL = 50 Ω to VCC; Refer to Figure 7-3138160203Khz
D1, D2 average switching Frequency (SN6505B)RL = 50 Ω to VCC; Refer to Figure 7-3.363424517kHz
F(EXT)External clock frequency on CLK pin (SN6505A)100600kHz
External clock frequency on CLK pin (SN6505B)1001600kHz
OUTPUT STAGE
DMMAverage ON time mismatch between D1 and D2RL = 50 Ω0%
R(ON)Output switch on resistanceVCC = 4.5 V, ID1,ID2 = 1 A0.160.25Ω
VCC = 2.8 V, ID1,ID2 = 1 A0.190.31Ω
VCC = 2.25 V, ID1,ID2 = 0.5 A0.210.45Ω
V(SLEW)Voltage slew rates on D1 and D2 for SN6505ARL = 50 Ω to VCC; Refer to Figure 7-348V/µs
I(SLEW)Current slew rates at D1 and D2 for SN6505ARL = 5 Ω through transformer;
Refer to Figure 7-4		11A/µs
V(SLEWHF)Voltage slew rates on D1 and D2 for SN6505BRL = 50 Ω to VCC; Refer to Figure 7-3152V/µs
I(SLEWHF)Current slew rates at D1 and D2 for SN6505BRL = 5 Ω through transformer;
Refer to Figure 7-4		41A/µs
ILIMCurrent clamp limit (2.8 V < VCC < 5.5V )1.421.752.15A
Current clamp limit (2.25 V < VCC < 2.8 V)0.651.85A
THERMAL SHUT DOWN
TSD+TSD turn on temperature154168181°C
TSD-TSD turn off temperature135150166°C
TSD-TSD hysteresis1317°C