JAJSL90 September   2022 SN6507-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics, SN6507-Q1
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Push-Pull Converter
      2. 8.3.2 Core Magnetization
      3. 8.3.3 Duty Cycle Control
      4.      Programmable Switching Frequency
      5. 8.3.4 Spread Spectrum Clocking
      6. 8.3.5 Slew Rate Control
      7. 8.3.6 Protection Features
        1. 8.3.6.1 Over Voltage Protection (OVP)
        2. 8.3.6.2 Over Current and Short Circuit Protection (OCP)
        3. 8.3.6.3 Under Voltage Lock-Out (UVLO)
        4. 8.3.6.4 Thermal Shut Down (TSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Start-Up Mode
        1. 8.4.1.1 Soft-Start
      2. 8.4.2 Operation Mode
      3. 8.4.3 Shutdown Mode
      4. 8.4.4 SYNC Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Pin Configuration
        2. 9.2.2.2 LDO Selection
        3. 9.2.2.3 Diode Selection
        4. 9.2.2.4 Capacitor and Inductor Selection
        5. 9.2.2.5 Transformer Selection
          1. 9.2.2.5.1 V-t Product Calculation
          2. 9.2.2.5.2 Turns Ratio Estimate
        6. 9.2.2.6 Low-Emissions Designs
      3. 9.2.3 Application Curves
      4. 9.2.4 System Examples
        1. 9.2.4.1 Higher Output Voltage Designs
        2. 9.2.4.2 Commercially-Available Transformers
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

Programmable Switching Frequency

SN6507-Q1 has an internal oscillator to set the switching frequency of the power stage. As the two power switches are out of phase, the oscillator frequency is twice of the actual switching frequency of each power switch. The duty cycle is fixed with 70 ns deadtime to avoid shoot-through. The duty cycle is changeable if duty cycle feature is enabled. Please refer to Section 8.3.3.

SN6507-Q1 has a wide switching frequency range from 100 kHz up to 2 MHz, which is pin-programmable through a resistor (RCLK) to GND. Below table lists the value of RCLK to achieve certain operating frequencies (fSW). The choice of switching frequency is a trade-off between power efficiency and size of capacitive and inductive components. For example, when operating at higher switching frequency, the size of the transformer and inductor is reduced, resulting in a smaller design footprint and lower cost. However, higher frequency increases switching losses and consequently degrades the overall power supply efficiency.

Table 8-1 Recommended 1% RCLK values and fSW Look-up Table
RCLKfSW (Typical)

111 kΩ

105 kHz

21 kΩ

523 kHz

9.6 kΩ

1.07 MHz

4.1 kΩ

2.13 MHz
0 kΩ (Short to GND)Default (1 MHz)

Figure 8-6 can also be used to estimate the programmable switching frequency, fSW, using an external resistor value, RCLK, where RCLK is in kΩ and fSW is in kHz:

Figure 8-6 Approximate SN6507-Q1 Switching Frequency, FSW, for RCLK Range

If CLK pin is shorted to GND, the part switches at its default frequency, FSW. CLK pin floating is not a valid state of operation and will cause the part to stop switching until an external clock signal is present.