JAJSPG7B April   1998  – January 2023 SN65ALS1176

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics - Driver
    5. 6.5 Switching Characteristics - Driver
    6. 6.6 Symbol Equivalents
    7. 6.7 Electrical Characteristics - Receiver
    8. 6.8 Switching Characteristics - Receiver
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
サーマルパッド・メカニカル・データ
発注情報

7 Parameter Measurement Information

GUID-20220712-SS0I-8FNP-TQCB-GJ0PFM5GPQKG-low.png Figure 7-1 Driver VOD2 and VOC Test Circuit
GUID-20220712-SS0I-4L9J-89D7-CXQCDKXRVRNM-low.png Figure 7-2 Driver VOD3 Test Circuit
GUID-20220712-SS0I-HKQG-HVKV-SXT1JRZVJ6LZ-low.png
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
C. td(OD) = td(ODH) or td(ODL).
Figure 7-3 Driver Differential-Output Delay and Transition Times
GUID-20220712-SS0I-S8NH-Q56S-BWCKCT05WMDC-low.png
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 7-4 Driver Enable and Disable Times
GUID-20220712-SS0I-SDRV-N7G1-SGQCJ1DN3F18-low.png
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 7-5 Driver Enable and Disable Times
GUID-20220712-SS0I-C9JH-F3DL-TQNG9RXFGSNG-low.png Figure 7-6 Receiver VOH and VOL Test Circuit
GUID-20220712-SS0I-CR12-HP2C-XVBNB3KDPTZM-low.png
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
C. tpd = tPLH or tPHL.
Figure 7-7 Receiver Propagation-Delay Times
GUID-20220712-SS0I-TN5K-PDNL-GJNLFN8PZQZJ-low.png
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 7-8 Receiver Output Enable and Disable Times