JAJSPG7B April   1998  – January 2023 SN65ALS1176

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics - Driver
    5. 6.5 Switching Characteristics - Driver
    6. 6.6 Symbol Equivalents
    7. 6.7 Electrical Characteristics - Receiver
    8. 6.8 Switching Characteristics - Receiver
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
サーマルパッド・メカニカル・データ
発注情報

6.5 Switching Characteristics - Driver

over recommended ranges of supply voltage and operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP#GUID-71955D15-290F-4D2F-B6E5-9ECE2B7809F9 MAX UNIT
td(OD) Differential output delay time

RL = 54 Ω

See GUID-70085789-1B7D-47A3-A437-48F4601574B3.html#FIG_VKW_BVY_D5B

 CL = 50 pF, 15 ns
tsk(p) Pulse skew#GUID-7CB6C435-59BF-45F8-826A-E7C99DF2368C 0 2 ns
tt(OD) Differential output transition time 8 ns
tPZH Output enable time to high level

RL = 110 Ω

See GUID-70085789-1B7D-47A3-A437-48F4601574B3.html#FIG_ED1_CVY_D5B

 CL = 50 pF, 80 ns
tPZL Output enable time to low level

RL = 110 Ω

See GUID-70085789-1B7D-47A3-A437-48F4601574B3.html#FIG_DYD_CVY_D5B

 CL = 50 pF, 30 ns
tPHZ Output disable time from high level

RL = 110 Ω

See GUID-70085789-1B7D-47A3-A437-48F4601574B3.html#FIG_ED1_CVY_D5B

 CL = 50 pF, 50 ns
tPLZ Output disable time from low level

RL = 110 Ω

See GUID-70085789-1B7D-47A3-A437-48F4601574B3.html#FIG_DYD_CVY_D5B

 CL = 50 pF, 30 ns
(1) All typical values are at VCC = 5 V, TA = 25°C
(2) Pulse skew is defined as the |tPLH– tPHL| of each channel of the same device.