JAJSFC7C September   2015  – July 2016 SN65DP149 , SN75DP149

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      DP149マザーボード・アプリケーションの構造
      2.      DP149ドングル・アプリケーションの構造
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Electrical Characteristics
    6. 7.6  Differential Input Electrical Characteristics
    7. 7.7  HDMI and DVI TMDS Output Electrical Characteristics
    8. 7.8  DDC, and I2C Electrical Characteristics
    9. 7.9  HPD Electrical Characteristics
    10. 7.10 HDMI and DVI Main Link Switching Characteristics
    11. 7.11 HPD Switching Characteristics
    12. 7.12 DDC and I2C Switching Characteristics
    13. 7.13 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reset Implementation
      2. 9.3.2 Operation Timing
      3. 9.3.3 Input Lane Swap and Polarity Working
      4. 9.3.4 Main Link Inputs
      5. 9.3.5 Main Link Inputs Debug Tools
      6. 9.3.6 Receiver Equalizer
      7. 9.3.7 Termination Impedance Control
      8. 9.3.8 TMDS Outputs
        1. 9.3.8.1 Pre-Emphasis/De-Emphasis
    4. 9.4 Device Functional Modes
      1. 9.4.1 Retimer Mode
      2. 9.4.2 Redriver Mode
      3. 9.4.3 DDC Functional Description
    5. 9.5 Register Maps
      1. 9.5.1 DP-HDMI Adaptor ID Buffer
      2. 9.5.2 Local I2C Interface Overview
      3. 9.5.3 I2C Control Behavior
      4. 9.5.4 I2C Control and Status Registers
        1. 9.5.4.1 Bit Access Tag Conventions
        2. 9.5.4.2 CSR Bit Field Definitions
          1. 9.5.4.2.1 ID Registers
          2. 9.5.4.2.2 Misc Control
          3. 9.5.4.2.3 HDMI Control
          4. 9.5.4.2.4 Equalization Control Register
          5. 9.5.4.2.5 EyeScan Control Register
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Use Case of SNx5DP149
      2. 10.1.2 DDC Pullup Resistors
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 System Example
      1. 10.3.1 Compliance Testing
  11. 11Power Supply Recommendations
    1. 11.1 Power Management
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連リンク
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.5.4.2.2 Misc Control

Table 7. Misc Control

ADDRESS BIT DEFAULT DESCRIPTION ACCESS
09h 7 1’b0 SWAP_EN: This field enables swapping the input main link lanes
0 – Disable (default)
1 – Enable
Note: field is loaded from SWAP/POL pin; Writes ignored when I2C_EN/PIN = 0		 RWU
6 1’b0 LANE_POLARITY: swaps the input data and clock lanes polarity.
0 – Disabled: No polarity swap
1 – Swaps the input data and clock lane polarity
Note: field is loaded from SWAP/POL pin; Writes ignored when I2C_EN/PIN = 0. This feature is only valid when in retimer mode. 		RWU
5:4 2'b00 Reserved R
3 1’b0 PD_EN
0 – Normal working (default)
1 – Forced power-down by I2C, lowest power state		 RW
2 1’b0 HPD_AUTO_PWRDWN_DISABLE
0 – Automatically enters power down mode based on HPD_SNK (default)
1 – Will not automatically enter power mode based upon HPD_SNK		 RW
1:0 2’b10 I2C_DR_CTL. I2C data rate supported for configuring device
00 – 5-kbps
01 – 10-kbps
10 – 100-kbps (default)
11 – 400-kbps (Note: HPD_AUTO_PWRDWN_DISABLE must be set before enabling 400 Kbps mode) 		RW
0Ah 7 1’b0 Application Mode Selection
0 – Source (default) - Set the adaptive EQ mid point to between 6.5-dB and 7.5-dB
1 – Sink - Sets the adaptive EQ starting point to between 12-dB and 13-dB		 RW
6 1’b0 HPDSNK_GATE_EN: This field sets the functional relationship between HPD_SNK and HPD_SRC.
0 – HPD_SNK passed through to the HPD_SRC (default)
1 – HPD_SNK will not pass through to the HPD_SRC.		 RW
5 1’b1 EQ_ADA_EN: this field enables the equalizer working state.
0 – Fixed EQ
1 – Adaptive EQ (default)
Writes are ignored when I2C_EN/PIN = 0		 RWU
4 1’b1 EQ_EN: this field enables the receiver equalizer.
0 – EQ disabled
1 – EQ enable (default) 		RW
3 1’b0 Reserved RW
2 1’b0 APPLY_RXTX_CHANGES , Self clearing write-only bit. Writing a 1 to this bit will apply new slew, tx_term, twpst1, eqen, eqadapten, swing, eqftc, eqlev settings to the clock and data lanes. Writes to the respective registers do not take immediate effect. This bit does not need to be written if I2C configuration occurs while OE or hpd_sink are low, I2C power down is active. W
1:0 2’b01 DEV_FUNC_MODE: This field selects the device working function mode.
00 – Redriver mode across full range 250 Mbps to 3.4-Gbps
01 - Automatic redriver to retimer crossover at 1.0 Gbps (default)
10 - Reserved
11 - Retimer mode across full range 250 Mbps to 3.4-Gbps		 RW
When changing crossover point, need to toggle PD_EN or toggle external HPD_SNK.

Mode Selection Definition: This bit lets the receiver know where the device is located in a system for the purpose of centering the AEQ point. The SNx5DP149 is targeting the source application, so the default value is 0, which will center the EQ at 6.5 to 7.5-dB , see Table 9. If the SNx5DP149 is in a dock or sink application, the value should be changed to a value of 1, which will center the EQ at 12 to 13-dB .