JAJSF94F July   2015  – May 2018 SN65DP159 , SN75DP159

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      DP159マザーボード・アプリケーションの構造
      2.      DP159ドングル・アプリケーションの構造
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Electrical Characteristics
    6. 7.6  Differential Input Electrical Characteristics
    7. 7.7  HDMI and DVI TMDS Output Electrical Characteristics
    8. 7.8  AUX, DDC, and I2C Electrical Characteristics
    9. 7.9  HPD Electrical Characteristics
    10. 7.10 HDMI and DVI Main Link Switching Characteristics
    11. 7.11 AUX Switching Characteristics (Only for RGZ Package)
    12. 7.12 HPD Switching Characteristics
    13. 7.13 DDC and I2C Switching Characteristics
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reset Implementation
      2. 9.3.2 Operation Timing
      3. 9.3.3 I2C-over-AUX to DDC Bridge (SNx5DP159 48-Pin Package Version Only)
      4. 9.3.4 Input Lane Swap and Polarity Working
      5. 9.3.5 Main Link Inputs
      6. 9.3.6 Main Link Inputs Debug Tools
      7. 9.3.7 Receiver Equalizer
      8. 9.3.8 Termination Impedance Control
      9. 9.3.9 TMDS Outputs
        1. 9.3.9.1 Pre-Emphasis/De-Emphasis
    4. 9.4 Device Functional Modes
      1. 9.4.1 Retimer Mode
      2. 9.4.2 Redriver Mode
      3. 9.4.3 DDC Training for HDMI2.0 Data Rate Monitor
      4. 9.4.4 DDC Functional Description
    5. 9.5 Register Maps
      1. 9.5.1 DP-HDMI Adaptor ID Buffer
      2. 9.5.2 Local I2C Interface Overview
      3. 9.5.3 I2C Control Behavior
      4. 9.5.4 I2C Control and Status Registers
        1. 9.5.4.1 Bit Access Tag Conventions
        2. 9.5.4.2 CSR Bit Field Definitions
          1. 9.5.4.2.1 ID Registers
          2. 9.5.4.2.2 Misc Control
          3. 9.5.4.2.3 HDMI Control
          4. 9.5.4.2.4 Equalization Control Register
          5. 9.5.4.2.5 EyeScan Control Register
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Use Case of SNx5DP159
      2. 10.1.2 DDC Pullup Resistors
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
    3. 10.3 System Example
      1. 10.3.1 Compliance Testing
  11. 11Power Supply Recommendations
    1. 11.1 Power Management
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
    3. 12.3 Thermal Considerations
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連リンク
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7 HDMI and DVI TMDS Output Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH Single-ended high level output voltage Data rate ≤ 1.65-Gbps; PRE_SEL = NC; TX_TERM_CTL = H; SLEW_CTL = H; OE = H; DR = 750-Mbps, VSadj = 7.06-kΩ VCC – 10 VCC + 10 mV
1.65-Gbps < Data rate ≤ 3.4-Gbps; PRE_SEL = NC; TX_TERM_CTL = H; SLEW_CTL = H; OE = H; DR = 2.97-Gbps, VSadj = 7.06-kΩ VCC – 200 VCC + 10
VOH Single-ended high level output voltage 3.4-Gbps < Data rate < 6 Gbps; PRE_SEL = NC; TX_TERM_CTL = L; SLEW_CTL = H; OE = H; DR = 6-Gbps, VSadj = 7.06-kΩ VCC – 400 VCC + 10 mV
VOL Single-ended low level output voltage Data rate ≤ 1.65-Gbps; PRE_SEL = NC; TX_TERM_CTL = H; SLEW_CTL = H; OE = H; DR = 750-Mbps, VSadj = 7.06-kΩ VCC – 600 VCC – 400 mV
1.65-Gbps < Data rate ≤ 3.4-Gbps; PRE_SEL = NC; TX_TERM_CTL = H; SLEW_CTL = H; OE = H; DR = 2.97-Gbps, VSadj = 7.06-kΩ VCC – 700 VCC – 400
VOL Single-ended low level output voltage 3.4-Gbps < Data rate < 6-Gbps; PRE_SEL = NC; TX_TERM_CTL = L; SLEW_CTL = H; OE = H; DR = 6-Gbps VCC – 1000 VCC – 400 mV
VSWING_DA Single-ended output voltage swing on data lane PRE_SEL = NC; TX_TERM_CTL = H/NC/L; SLEW_CTL = H; OE = H; DR = 270-Mbs/2.97/6Gbps VSadj = 7.06-kΩ 400 500 600 mV
VSWING_CLK Single-ended output voltage swing on clock lane Data rate ≤ 3.4-Gbps; PRE_SEL = NC; TX_TERM_CTL = H; SLEW_CTL = H; OE = H; VSadj = 7.06-kΩ 400 500 600 mV
Data rate > 3.4-Gbps; PRE_SEL = NC; TX_TERM_CTL = NC; SLEW_CTL = H; OE = H; VSadj = 7.06-kΩ 200 300 400
ΔVSWING Change in single-end output voltage swing per 100 Ω ΔVsadj 20 mV
ΔVOCM(SS) Change in steady state output common mode voltage between logic levels –5 5 mV
VOD(PP) Output differential voltage before pre-emphasis Vsadj = 7.06-kΩ; PRE_SEL = Z, See Figure 8 800 1200 mV
VOD(SS) Steady-state output differential voltage Vsadj = 7.06-kΩ; PRE_SEL = L, See Figure 9 600 1050 mV
ILEAK Failsafe condition leakage current VCC = 0-V; VDD = 0-V; output pulled to 3.3 V through 50-Ω resistors 45 µA
IOS Short circuit current limit Main link output shorted to GND 50 mA
RTERM Source termination resistance for HDMI 2.0 75 150 Ω