JAJSF94F July   2015  – May 2018 SN65DP159 , SN75DP159

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      DP159マザーボード・アプリケーションの構造
      2.      DP159ドングル・アプリケーションの構造
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Electrical Characteristics
    6. 7.6  Differential Input Electrical Characteristics
    7. 7.7  HDMI and DVI TMDS Output Electrical Characteristics
    8. 7.8  AUX, DDC, and I2C Electrical Characteristics
    9. 7.9  HPD Electrical Characteristics
    10. 7.10 HDMI and DVI Main Link Switching Characteristics
    11. 7.11 AUX Switching Characteristics (Only for RGZ Package)
    12. 7.12 HPD Switching Characteristics
    13. 7.13 DDC and I2C Switching Characteristics
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reset Implementation
      2. 9.3.2 Operation Timing
      3. 9.3.3 I2C-over-AUX to DDC Bridge (SNx5DP159 48-Pin Package Version Only)
      4. 9.3.4 Input Lane Swap and Polarity Working
      5. 9.3.5 Main Link Inputs
      6. 9.3.6 Main Link Inputs Debug Tools
      7. 9.3.7 Receiver Equalizer
      8. 9.3.8 Termination Impedance Control
      9. 9.3.9 TMDS Outputs
        1. 9.3.9.1 Pre-Emphasis/De-Emphasis
    4. 9.4 Device Functional Modes
      1. 9.4.1 Retimer Mode
      2. 9.4.2 Redriver Mode
      3. 9.4.3 DDC Training for HDMI2.0 Data Rate Monitor
      4. 9.4.4 DDC Functional Description
    5. 9.5 Register Maps
      1. 9.5.1 DP-HDMI Adaptor ID Buffer
      2. 9.5.2 Local I2C Interface Overview
      3. 9.5.3 I2C Control Behavior
      4. 9.5.4 I2C Control and Status Registers
        1. 9.5.4.1 Bit Access Tag Conventions
        2. 9.5.4.2 CSR Bit Field Definitions
          1. 9.5.4.2.1 ID Registers
          2. 9.5.4.2.2 Misc Control
          3. 9.5.4.2.3 HDMI Control
          4. 9.5.4.2.4 Equalization Control Register
          5. 9.5.4.2.5 EyeScan Control Register
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Use Case of SNx5DP159
      2. 10.1.2 DDC Pullup Resistors
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
    3. 10.3 System Example
      1. 10.3.1 Compliance Testing
  11. 11Power Supply Recommendations
    1. 11.1 Power Management
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
    3. 12.3 Thermal Considerations
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連リンク
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Parameter Measurement Information

SN65DP159 SN75DP159 tim_TMDS_main_SLLSEJ2.gifFigure 4. TMDS Main Link Test Circuit
SN65DP159 SN75DP159 tim_IO_SLLSEJ2.gifFigure 5. Input and Output Timing Measurements
SN65DP159 SN75DP159 tim_HDMI_DVI_sink_SLLSEJ2.gifFigure 6. HDMI and DVI Sink TMDS Output Skew Measurements
SN65DP159 SN75DP159 tim_TMDS_main_mode_SLLSEJ2.gifFigure 7. TMDS Main Link Common Mode Measurements
SN65DP159 SN75DP159 sllsej2_figure7.gifFigure 8. Output Differential Waveform 0 dB De-Emphasis
SN65DP159 SN75DP159 PRE_SEL_L_sllsej2.gifFigure 9. PRE_SEL = L for –2-dB De-Emphasis
SN65DP159 SN75DP159 alt_TMDS_output_2_SLLSEJ2.gif
1. The FR4 trace between TTP1 and TTP2 is designed to emulate 1-8” of FR4, AC coupling cap, connector and another 1-2” of FR4. Trace width – 4 mils. 100-Ω differential impedance.
2. All jitter is measured at a BER of 10-9.
3. Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP1.
4. AVCC = 3.3-V
5. RT = 50-Ω
6. The input signal from parallel bit error rate tester (BERT) does not have any pre-emphasis. Refer to Recommended Operating Conditions.
Figure 10. TMDS Output Jitter Measurement
SN65DP159 SN75DP159 gr_input_eyemask_2_SLLSEJ2.gifFigure 11. Post EQ Input Eye Mask at TTP2_EQ
TMDS DATA RATE (Gbps) H (Tbit) V (mV)
3.4 < DR < 3.712 0.6 335
3.712 < DR < 5.94 –0.0332Rbit2 + 0.2312Rbit + 0.1998 –19.66Rbit2 + 106.74Rbit + 209.58
5.94 ≤ DR ≤ 6.0 0.4 150
Figure 12. Output Eye Mask at TTP4_EQ
SN65DP159 SN75DP159 cir_HPD_test_SLLSEJ2.gifFigure 13. HPD Test Circuit
SN65DP159 SN75DP159 tim_HPD_1_SLLSEJ2.gifFigure 14. HPD Timing Diagram Number 1
SN65DP159 SN75DP159 tim_HPD_logic_to_SLLSEJ2.gifFigure 15. HPD Logic Disconnect Timeout
SN65DP159 SN75DP159 tim_start_stop_cond_SLLSEJ2.gifFigure 16. Start and Stop Condition Timing
SN65DP159 SN75DP159 tim_SCL_SDA_SLLSEJ2.gifFigure 17. SCL and SDA Timing
SN65DP159 SN75DP159 tim_DDC_source2sink_SLLSEJ2.gifFigure 18. DDC Propagation Delay – Source to Sink
SN65DP159 SN75DP159 tim_DDC_sink2source_SLLSEJ2.gifFigure 19. DDC Propagation Delay – Sink to Source