JAJSF94F July   2015  – May 2018 SN65DP159 , SN75DP159

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      DP159マザーボード・アプリケーションの構造
      2.      DP159ドングル・アプリケーションの構造
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Electrical Characteristics
    6. 7.6  Differential Input Electrical Characteristics
    7. 7.7  HDMI and DVI TMDS Output Electrical Characteristics
    8. 7.8  AUX, DDC, and I2C Electrical Characteristics
    9. 7.9  HPD Electrical Characteristics
    10. 7.10 HDMI and DVI Main Link Switching Characteristics
    11. 7.11 AUX Switching Characteristics (Only for RGZ Package)
    12. 7.12 HPD Switching Characteristics
    13. 7.13 DDC and I2C Switching Characteristics
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reset Implementation
      2. 9.3.2 Operation Timing
      3. 9.3.3 I2C-over-AUX to DDC Bridge (SNx5DP159 48-Pin Package Version Only)
      4. 9.3.4 Input Lane Swap and Polarity Working
      5. 9.3.5 Main Link Inputs
      6. 9.3.6 Main Link Inputs Debug Tools
      7. 9.3.7 Receiver Equalizer
      8. 9.3.8 Termination Impedance Control
      9. 9.3.9 TMDS Outputs
        1. 9.3.9.1 Pre-Emphasis/De-Emphasis
    4. 9.4 Device Functional Modes
      1. 9.4.1 Retimer Mode
      2. 9.4.2 Redriver Mode
      3. 9.4.3 DDC Training for HDMI2.0 Data Rate Monitor
      4. 9.4.4 DDC Functional Description
    5. 9.5 Register Maps
      1. 9.5.1 DP-HDMI Adaptor ID Buffer
      2. 9.5.2 Local I2C Interface Overview
      3. 9.5.3 I2C Control Behavior
      4. 9.5.4 I2C Control and Status Registers
        1. 9.5.4.1 Bit Access Tag Conventions
        2. 9.5.4.2 CSR Bit Field Definitions
          1. 9.5.4.2.1 ID Registers
          2. 9.5.4.2.2 Misc Control
          3. 9.5.4.2.3 HDMI Control
          4. 9.5.4.2.4 Equalization Control Register
          5. 9.5.4.2.5 EyeScan Control Register
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Use Case of SNx5DP159
      2. 10.1.2 DDC Pullup Resistors
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
    3. 10.3 System Example
      1. 10.3.1 Compliance Testing
  11. 11Power Supply Recommendations
    1. 11.1 Power Management
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
    3. 12.3 Thermal Considerations
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連リンク
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.1.2 DDC Pullup Resistors

NOTE

This section is for information only and subject to change depending upon system implementation.

The pullup resistor value is determined by two requirements:

  1. The maximum sink current of the I2C buffer:
    The maximum sink current is 3-mA or slightly higher for an I2C driver supporting standard-mode I2C[4] operation.
    2. Equation 1. SN65DP159 SN75DP159 Eq1_Rup_sllsej2.gif
  2. The maximum transition time on the bus:
    The maximum transition time, T, of an I2C bus is set by an RC time constant, where R is the pullup resistor value, and C is the total load capacitance. The parameter, k, can be calculated from Equation 3 by solving for t, the times at which certain voltage thresholds are reached. Different input threshold combinations introduce different values of t. Table 11 summarizes the possible values of k under different threshold combinations.
    3. Equation 2. SN65DP159 SN75DP159 Eq2_T_sllsej2.gif
    Equation 3. SN65DP159 SN75DP159 Eq3_Vt_sllsej2.gif

Table 11. Value k Upon Different Input Threshold Voltages

Vth–\Vth+ 0.7 VCC 0.65 VCC 0.6 VCC 0.55 VCC 0.5 VCC 0.45 VCC 0.4 VCC 0.35 VCC 0.3 VCC
0.1 VCC 1.0986 0.9445 0.8109 0.6931 0.5878 0.4925 0.4055 0.3254 0.2513
0.15 VCC 1.0415 0.8873 0.7538 0.6360 0.5306 0.4353 0.3483 0.2683 0.1942
0.2 VCC 0.9808 0.8267 0.6931 0.5754 0.4700 0.3747 0.2877 0.2076 0.1335
0.25 VCC 0.9163 0.7621 0.6286 0.5108 0.4055 0.3102 0.2231 0.1431 0.0690
0.3 VCC 0.8473 0.6931 0.5596 0.4418 0.3365 0.2412 0.1542 0.0741

From Equation 1, Rup(min) = 5.5-V / 3-mA = 1.83-kΩ to operate the bus under a 5-V pullup voltage and provide less than 3-mA when the I2C device is driving the bus to a low state. If a higher sink current, for example 4 mA, is allowed, Rup(min) can be as low as 1.375-kΩ.

If DDC is working at a standard mode of 100-Kbps, the maximum transition time, T, is fixed, 1 μs, and using the k values from Table 11, the recommended maximum total resistance of the pullup resistors on an I2C bus can be calculated for different system setups. If DDC is working in a fast mode of 400-kbps, the transition time should be set at 300 ns, according to I2C[4] specification.

To support the maximum load capacitance specified in the HDMI specification, Ccable(max) = 700-pF, Csource = 50-pF, Ci = 50-pF, and R(max) can be calculated as shown in Table 12.

Table 12. Pullup Resistor Upon Different Threshold Voltages and 800-pF Loads

Vth–\Vth+ 0.7 VCC 0.65 VCC 0.6 VCC 0.55 VCC 0.5 VCC 0.45 VCC 0.4 VCC 0.35 VCC 0.3 VCC UNIT
0.1 VCC 1.14 1.32 1.54 1.8 2.13 2.54 3.08 3.84 4.97 kΩ
0.15 VCC 1.2 1.41 1.66 1.97 2.36 2.87 3.59 4.66 6.44 kΩ
0.2 VCC 1.27 1.51 1.8 2.17 2.66 3.34 4.35 6.02 9.36 kΩ
0.25 VCC 1.36 1.64 1.99 2.45 3.08 4.03 5.6 8.74 18.12 kΩ
0.3 VCC 1.48 1.8 2.23 2.83 3.72 5.18 8.11 16.87 — kΩ

To accommodate the 3-mA drive current specification, a narrower threshold voltage range is required to support a maximum 800-pF load capacitance for a standard-mode I2C bus.