JAJSF94F July   2015  – May 2018 SN65DP159 , SN75DP159

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      DP159マザーボード・アプリケーションの構造
      2.      DP159ドングル・アプリケーションの構造
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Electrical Characteristics
    6. 7.6  Differential Input Electrical Characteristics
    7. 7.7  HDMI and DVI TMDS Output Electrical Characteristics
    8. 7.8  AUX, DDC, and I2C Electrical Characteristics
    9. 7.9  HPD Electrical Characteristics
    10. 7.10 HDMI and DVI Main Link Switching Characteristics
    11. 7.11 AUX Switching Characteristics (Only for RGZ Package)
    12. 7.12 HPD Switching Characteristics
    13. 7.13 DDC and I2C Switching Characteristics
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reset Implementation
      2. 9.3.2 Operation Timing
      3. 9.3.3 I2C-over-AUX to DDC Bridge (SNx5DP159 48-Pin Package Version Only)
      4. 9.3.4 Input Lane Swap and Polarity Working
      5. 9.3.5 Main Link Inputs
      6. 9.3.6 Main Link Inputs Debug Tools
      7. 9.3.7 Receiver Equalizer
      8. 9.3.8 Termination Impedance Control
      9. 9.3.9 TMDS Outputs
        1. 9.3.9.1 Pre-Emphasis/De-Emphasis
    4. 9.4 Device Functional Modes
      1. 9.4.1 Retimer Mode
      2. 9.4.2 Redriver Mode
      3. 9.4.3 DDC Training for HDMI2.0 Data Rate Monitor
      4. 9.4.4 DDC Functional Description
    5. 9.5 Register Maps
      1. 9.5.1 DP-HDMI Adaptor ID Buffer
      2. 9.5.2 Local I2C Interface Overview
      3. 9.5.3 I2C Control Behavior
      4. 9.5.4 I2C Control and Status Registers
        1. 9.5.4.1 Bit Access Tag Conventions
        2. 9.5.4.2 CSR Bit Field Definitions
          1. 9.5.4.2.1 ID Registers
          2. 9.5.4.2.2 Misc Control
          3. 9.5.4.2.3 HDMI Control
          4. 9.5.4.2.4 Equalization Control Register
          5. 9.5.4.2.5 EyeScan Control Register
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Use Case of SNx5DP159
      2. 10.1.2 DDC Pullup Resistors
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
    3. 10.3 System Example
      1. 10.3.1 Compliance Testing
  11. 11Power Supply Recommendations
    1. 11.1 Power Management
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
    3. 12.3 Thermal Considerations
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連リンク
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.3.1 Compliance Testing

Compliance testing is very system design specific. Properly designing the system and configuring the DP159 can help pass transmitter compliance for the system. The following information is the starting point to help prepare for compliance test. As each system is different there are many features in the DP159 to help tune the circuit. These include VOD adjust by changing the Vsadj resistor value or using I2C. Other knobs to turn are pre/de-emphasis and slew rate control. Passing both HDMI2.0 and HDMI1.4b compliance is easier to accomplish when using I2C as this provides more fine tuning capability.

For the SNx5DP159RGZ:

Pin Strapping

HDMI2.0 & HDMI1.4b

Vsadj Resistor = 7.06-kΩ

PRE_SEL = NC for 0-dB

TX_TERM_CTL = NC for Auto Select

SLEW_CTL = NC

I2C Control

HDMI2.0 & HDMI1.4b

Vsadj Resistor = 7.06 kΩ

PRE_SEL = Reg0Ch[1:0] = 00 (labeled HDMI_TWPST)

TX_TERM_CTL =

  • Reg0Bh[4:3] = 00 → No term; HDMI1.4b < 2Gbps (This may be best value for all HDMI1.4b)
  • Reg0Bh[4:3] = 01 → 150 to 300 Ω; HDMI1.4b > 2Gbps
  • Reg0Bh[4:3] = 11 → 75 to 150 Ω; HDMI2.0

SLEW_CTL = Reg0Bh[7:6] = 10

For the SNx5DP159RSB:

Pin Strapping

HDMI2.0 and HDMI1.4b

Vsadj Resistor = 6.5 kΩ

PRE_SEL = L for –2 dB

TX_TERM_CTL = NC for Auto Select

SLEW_CTL = NC

I2C

HDMI2.0

Vsadj Resistor = 6.5 kΩ

PRE_SEL = Reg0Ch[1:0] = 01 (labeled HDMI_TWPST)

TX_TERM_CTL = Reg0Bh[4:3] = 11

SLEW_CTL = Reg0Bh[7:6] = 10

HDMI1.4b

Vsadj Resistor = 6.5 kΩ

VSWING_DATA & VSWING_CLK to -7% = Reg0Ch[7:2] = 111111

PRE_SEL = Reg0Ch[1:0] = 00: (Labeled HDMI_TWPST)

TX_TERM_CTL: Reg0Bh[4:3]

  • <2 Gbps = 00 for no termination (This may be best value for all HDMI1.4b)
  • >2 Gbps and < 3.4 Gbps = 01 for 150 to 300 Ω

SLEW_CTL = Reg0Bh[7:6] = 10