JAJSF94F July   2015  – May 2018 SN65DP159 , SN75DP159

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      DP159マザーボード・アプリケーションの構造
      2.      DP159ドングル・アプリケーションの構造
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Electrical Characteristics
    6. 7.6  Differential Input Electrical Characteristics
    7. 7.7  HDMI and DVI TMDS Output Electrical Characteristics
    8. 7.8  AUX, DDC, and I2C Electrical Characteristics
    9. 7.9  HPD Electrical Characteristics
    10. 7.10 HDMI and DVI Main Link Switching Characteristics
    11. 7.11 AUX Switching Characteristics (Only for RGZ Package)
    12. 7.12 HPD Switching Characteristics
    13. 7.13 DDC and I2C Switching Characteristics
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reset Implementation
      2. 9.3.2 Operation Timing
      3. 9.3.3 I2C-over-AUX to DDC Bridge (SNx5DP159 48-Pin Package Version Only)
      4. 9.3.4 Input Lane Swap and Polarity Working
      5. 9.3.5 Main Link Inputs
      6. 9.3.6 Main Link Inputs Debug Tools
      7. 9.3.7 Receiver Equalizer
      8. 9.3.8 Termination Impedance Control
      9. 9.3.9 TMDS Outputs
        1. 9.3.9.1 Pre-Emphasis/De-Emphasis
    4. 9.4 Device Functional Modes
      1. 9.4.1 Retimer Mode
      2. 9.4.2 Redriver Mode
      3. 9.4.3 DDC Training for HDMI2.0 Data Rate Monitor
      4. 9.4.4 DDC Functional Description
    5. 9.5 Register Maps
      1. 9.5.1 DP-HDMI Adaptor ID Buffer
      2. 9.5.2 Local I2C Interface Overview
      3. 9.5.3 I2C Control Behavior
      4. 9.5.4 I2C Control and Status Registers
        1. 9.5.4.1 Bit Access Tag Conventions
        2. 9.5.4.2 CSR Bit Field Definitions
          1. 9.5.4.2.1 ID Registers
          2. 9.5.4.2.2 Misc Control
          3. 9.5.4.2.3 HDMI Control
          4. 9.5.4.2.4 Equalization Control Register
          5. 9.5.4.2.5 EyeScan Control Register
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Use Case of SNx5DP159
      2. 10.1.2 DDC Pullup Resistors
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
    3. 10.3 System Example
      1. 10.3.1 Compliance Testing
  11. 11Power Supply Recommendations
    1. 11.1 Power Management
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
    3. 12.3 Thermal Considerations
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連リンク
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RGZ Package
48-Pin VQFN
Top View
RSB Package
40-Pin WQFN
Top View

Pin Functions

PIN(2) I/O DESCRIPTION(1)
SIGNAL NAME RGZ RSB
MAIN LINK INPUT PINS (FAIL SAFE)
IN_D2p 2 1 I Channel 2 differential input
IN_D2n 3 2
IN_D1p 5 4 I Channel 1 differential input
IN_D1n 6 5
IN_D0p 8 6 I Channel 0 differential input
IN_D0n 9 7
IN_CLKp 11 9 I Clock differential input
IN_CLKn 12 10
MAIN LINK OUTPUT PINS (FAIL SAFE)
OUT_D2n 34 29 O TMDS data 2 differential output
OUT_D2p 35 30
OUT_D1n 31 26 O TMDS data 1 differential output
OUT_D1p 32 27
OUT_D0n 28 24 O TMDS data 0 differential output
OUT_D0p 29 25
OUT_CLKn 25 21 O TMDS data clock differential output
OUT_CLKp 26 22
HOT PLUG DETECT PINS
HPD_SRC 4 3 O Hot plug detect output
HPD_SNK 33 28 I (Failsafe) Hot plug detect input
AUXILIARY/DDC DATA PINS
AUX_SRCp 45 N/A I/O Source side bidirectional DisplayPort auxiliary for I2C-over-AUX (DP159RGZ only)
AUX_SRCn 44 N/A
SDA_SRC 47 39 I/O (Failsafe) Source side TMDS port bidirectional DDC data line
SCL_SRC 46 38
SDA_SNK 39 33 I/O (Failsafe) Sink side TMDS port bidirectional DDC data lines
SCL_SNK 38 32
CONTROL PINS
OE 42 36 I Operation enable/reset pin
OE = L: Power-down mode
OE = H: Normal operation
Internal weak pullup: Resets device when transitions from H to L
NC (2) 17 N/A I No connect
CEC_EN(2) 18 N/A O CEC control pin for Dongle applications
SLEW_CTL 40 34 I
3
level (1) 		Slew rate control when I2C_EN/PIN = Low.
SLEW_CTL = H, fastest data rate
SLEW_CTL = L, 5 ps slow
SLEW_CTL = No Connect, 10 ps slow
When I2C_EN/PIN = High Slew rate is controlled through I2C[4]
PRE_SEL 20 16 I
3
level (1) 		De-emphasis pin strap when I2C_EN/PIN = Low.
PRE_SEL = L: - 2 dB de-emphasis
PRE_SEL = No Connect: 0 dB
PRE_SEL = H: Reserved
EQ_SEL/A0 21 17 I
3
level (1) 		Input Receive Equalization pin strap when I2C_EN/PIN = Low
EQ_SEL = L: Fixed EQ at 7.5 dB
EQ_SEL = No Connect: Adaptive EQ
EQ_SEL = H: Fixed at 14 dB
When I2C_EN/PIN = High
Address bit 1
Note: (3 level for pin strap programming but 2 level when I2C[4] address)
I2C_EN/PIN 10 8 I I2C_EN/PIN = High; puts device into I2C control mode
I2C_EN/PIN = Low; puts device into pin strap mode
SCL_CTL 15 13 I I2C clock signal
Note: When I2C_EN/PIN = Low Pin strapping take priority and those functions cannot be changed by I2C
SDA_CTL 16 14 I/O I2C data signal
Note: When I2C_EN/PIN = Low Pin strapping take priority and those functions cannot be changed by I2C
Vsadj 22 18 I TMDS-compliant voltage swing control nominal resistor to GND
HDMI_SEL/A1 27 23 I HDMI_SEL when I2C_EN/PIN = Low
HDMI_SEL = High: Device configured for DVI
HDMI_SEL = Low: Device configured for HDMI (Adaptor ID block is readable through I2C[4] or I2C-over-AUX.
When I2C_EN/PIN = High
Address bit 2
Note: Weak internal pull down
TX_TERM_CTL(2) 36 N/A I
3
level (1) 		Transmit Termination Control when I2C_EN/PIN = Low
TX_TERM_CTL = H, No transmit termination
TX_TERM_CTL = L, Transmit termination impedance in 75 to about 150 Ω
TX_TERM_CTL = No Connect, automatically selects the termination impedance
Data rate (DR) > 3.4 Gbps – 75- to 150-Ω differential near end termination
2 Gbps < DR < 3.4 Gbps – 150- to 300-Ω differential near end termination
DR < 2 Gbps – no termination
Note: If left floating will be in automatic select mode.
SWAP/POL(2) 1 N/A I
3
level (1) 		Input lane SWAP and polarity control pin when I2C_EN/PIN = Low
SWAP/POL = H receive lane polarity swap (retimer mode only)
SWAP/POL = L receive lanes swap (retimer and redriver mode)
SWAP/POL = No Connect normal working
SUPPLY AND GROUND PINS
VCC 13, 43 11, 37 P 3.3-V power supply
VDD 14, 23, 24, 37, 48 12, 19, 20, 31, 40 P 1.1-V power supply
GND 7, 19, 41, 30, 15, 35 G Ground
Thermal Pad Connected to ground
(1) (H) Logic high (pin strapped to VCC through 65-kΩ resistor); (L) logic low (pin strapped to GND through 65-kΩ resistor); (for mid-level, no connect)
(2) Blue pin names are only in the SNx5DP159 RGZ package.