LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. Standard CSR Register (0x09)
Bit
Field
Type
Reset
Description
7:4
Reserved
R
0
Reserved
3:2
RXEQ_CLK
RW
0
This field selects the EQ level of the DACP/N. The value in this field will match the sampled state of EQ/SCL pin at the rising edge of RSTN. Software can change the value of this field at a later time.
00 – 0 dB (EQ/SCL pin = VIL)
01 – 2.5 dB (EQ/SCL pin = VIM)
10 – Reserved.
11 – 5 dB (EQ/SCL pin = VIH)
1:0
RXEQ_DATA
RW
0
This field selects the EQ level of the DA[3:0]P/N . The value in this field will match the sampled state of EQ/SCL pin at the rising edge of RSTN. Software can change the value of this field at a later time.
00 – 0 dB. (EQ/SCL pin = VIL)
01 – 2.5 dB (EQ/SCL pin = VIM)
10 – Reserved.
11 – 5 dB. (EQ/SCL pin = VIH)