JAJSDL3C March 2016 – August 2019 SN65DPHY440SS , SN75DPHY440SS
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BTA_TIMEOUT_HI | |||||||
RW | RW | RW | RW | RW | RW | RW | RW |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | BTA_TIMEOUT_HI | RW | 0xFF | This field represents the upper 8-bits of the 16-bit BTA_TIMEOUT register. Timer is reset to default state when BTA request is detected and is stopped when BTA is acknowledged. If BTA is not acknowledged before this timer expires, then DPHY440 will terminate BTA operation. This counter operates on the LPTX clock. Defaults to 0xFF. |