JAJSDL3D March   2016  – October 2024 SN65DPHY440SS , SN75DPHY440SS

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics, Power Supply
    6. 5.6 Electrical Characteristics
    7. 5.7 Timing Requirements
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 HS Receive Equalization
      2. 6.3.2 HS TX Edge Rate Control
      3. 6.3.3 TX Voltage Swing and Pre-Emphasis Control
      4. 6.3.4 Dynamic De-skew
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 LP Mode
      3. 6.4.3 ULPS Mode
      4. 6.4.4 HS Mode
    5. 6.5 Register Maps
      1. 6.5.1  BIT Access Tag Conventions
      2. 6.5.2  Standard CSR Registers (address = 0x000 - 0x07)
      3. 6.5.3  Standard CSR Register (address = 0x08)
      4. 6.5.4  Standard CSR Register (address = 0x09)
      5. 6.5.5  Standard CSR Register (address = 0x0A)
      6. 6.5.6  Standard CSR Register (address = 0x0B)
      7. 6.5.7  Standard CSR Register (address = 0x0D)
      8. 6.5.8  Standard CSR Register (address = 0x0E)
      9. 6.5.9  Standard CSR Register (address = 0x10) [reset = 0xFF]
      10. 6.5.10 Standard CSR Register (address = 0x11) [reset = 0xFF]
  8. 7 Application and Implementation
    1. 7.1 Application Information,
    2. 7.2 Typical Application, CSI-2 Implementations
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Reset Implementation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.2 Detailed Design Procedure

The typical example describes how to configure the VSADJ, PRE, EQ and ERC configuration pins of the DPHY440 device based on the board trace length between the Source (Camera) and DPHY440 and the DPHY440 and Sink (APU). Actual configuration settings might differ due to additional factors such as board layout, and connectors used in the signal path.

Though the data rate in this example is 1 Gbps, device is placed near to the Sink, with a short output trace of 1 inch. Consequently, the ERC pin can be configured to have a rise/fall time of 250 ps for the edge. Further, due to the short output trace, the PRE pin must be configured to a setting of 0 dB and the VSADJ to be 200 mV. The Application Curve in Figure 7-6 shows the FR-4 loss characteristics of a 10 mil wide, 12 inch long trace. From this plot, the input signal trace suffers a loss of 1.5 dB at 500 MHz. Thus, the EQ setting can be either 0 dB or 2.5 dB. All the configuration settings and their corresponding inputs are tabulated in Table 7-2.

Table 7-2 Configuration Pin Settings
PINSETTINGINPUT VALUE
VSADJ200 mVVIM
PRE0 dBVIM
EQ0 dB or 2.5 dBVIL or VIM
ERC250 psVIH

The configuration pins each have internal pull-up and pull-down resistors of 100 kΩ each. Thus, the recommendation is an external pull-up/pull-down resistors of about 10 kΩ each, to meet the requirement of the threshold levels for the VIL and VIH listed in the Electrical Characteristics table. The external resistors shown in Figure 7-2 should be populated to produce corresponding configuration settings, according to the list given in Table 7-3.

Table 7-3 Resistor Parameters
RESISTOR NAMEVALUE
R1Leave unpopulated
R2Leave unpopulated
R3Leave unpopulated
R4Leave unpopulated
R5Leave unpopulated
R610 kΩ (EQ = 0 dB) or
Leave unpopulated (EQ = 2.5 dB)
R710 kΩ
R8Leave unpopulated