JAJSCQ7A December 2016 – June 2018 SN65DSI84-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSI_CLK_DIVIDER | Reserved | REFCLK_MULTIPLIER | |||||
R/W | R | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | DSI_CLK_DIVIDER | R/W | 00000 | When CSR 0x0A.0 = ‘1’, this field controls the divider used to generate the LVDS output clock from the MIPI D-PHY Channel A HS continuous clock. When CSR 0x0A.0 = ‘0’, this field must be programmed to 00000.
00000 – LVDS clock = source clock (default) 00001 – Divide by 2 00010 – Divide by 3 00011 – Divide by 4 • • • 10111 – Divide by 24 11000 – Divide by 25 11001 through 11111 – Reserved |
2 | Reserved | R | ||
1-0 | REFCLK_MULTIPLIER | R/W | 00 | When CSR 0x0A.0 = ‘0’, this field controls the multiplier used to generate the LVDS output clock from the input REFCLK. When CSR 0x0A.0 = ‘1’, this field must be programmed to 00.
00 – LVDS clock = source clock (default) 01 – Multiply by 2 10 – Multiply by 3 11 – Multiply by 4 |